[PATCH RFC 4/5] KVM: PPC: Book3S HV: Work around XER[SO] bug in fake suspend mode

ode before doing the treclaim. This patch adds the code to do that. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 20 1 file changed, 16 insertions(+)

Re: [PATCH 3/3] powerpc/64s/idle: POWER9 ESL=0 stop avoid save/restore overhead

On Thu, Mar 01, 2018 at 09:57:34PM +1000, Nicholas Piggin wrote: > On Thu, 1 Mar 2018 00:04:39 +0530 > Vaidyanathan Srinivasan wrote: > > > * Nicholas Piggin [2017-11-18 00:08:07]: [snip] > > > diff --git a/arch/powerpc/platforms/powernv/idle.c > >

Re: [PATCH] KVM: PPC: Book3S HV: Fix guest time accounting with VIRT_CPU_ACCOUNTING_GEN

On Fri, Mar 02, 2018 at 11:51:56AM +0100, Laurent Vivier wrote: > Since commit 8b24e69fc47e ("KVM: PPC: Book3S HV: Close race with testing > for signals on guest entry"), if CONFIG_VIRT_CPU_ACCOUNTING_GEN is set, the > guest time is not accounted to guest time and user time, but instead to >

Re: [PATCH 02/20] KVM: PPC: Book3S PR: Fix broken select due to misspelling

On Mon, Feb 05, 2018 at 05:58:59AM +0100, Ulf Magnusson wrote: > On Mon, Feb 5, 2018 at 5:48 AM, Paul Mackerras <pau...@ozlabs.org> wrote: > > On Mon, Feb 05, 2018 at 02:21:14AM +0100, Ulf Magnusson wrote: > >> Commit 76d837a4c0f9 ("KVM: PPC: Book3S PR: Don't inclu

Re: [PATCH 02/20] KVM: PPC: Book3S PR: Fix broken select due to misspelling

RIES was > probably intended. > > Change PPC_SERIES to PPC_PSERIES. > > Discovered with the > https://github.com/ulfalizer/Kconfiglib/blob/master/examples/list_undefined.py > script. > > Signed-off-by: Ulf Magnusson <ulfali...@gmail.com> Acked-by: Paul Mackerras

Re: [PATCH v5 1/1] KVM: PPC: Book3S: Add MMIO emulation for VMX instructions

On Thu, Feb 01, 2018 at 04:15:39PM -0200, Jose Ricardo Ziviani wrote: > This patch provides the MMIO load/store vector indexed > X-Form emulation. > > Instructions implemented: > lvx: the quadword in storage addressed by the result of EA & > 0x___fff0 is loaded into VRT. > > stvx:

Re: [PATCH v5 0/1] Implements MMIO emulation for lvx/stvx instructions

On Thu, Feb 01, 2018 at 04:15:38PM -0200, Jose Ricardo Ziviani wrote: > v5: > - Fixed the mask off of the effective address > > v4: > - Changed KVM_MMIO_REG_VMX to 0xc0 because there are 64 VSX registers > > v3: > - Added Reported-by in the commit message > > v2: > -

Re: [RFC PATCH] powerpc/powernv: Provide a way to force a core into SMT4 mode

On Sat, Jan 27, 2018 at 10:27:35AM +1000, Nicholas Piggin wrote: > On Thu, 25 Jan 2018 16:05:12 +1100 > Paul Mackerras <pau...@ozlabs.org> wrote: > > > POWER9 processors up to and including "Nimbus" v2.2 have hardware > > bugs relating to transactional memor

Re: [RFC PATCH] powerpc/powernv: Provide a way to force a core into SMT4 mode

On Fri, Jan 26, 2018 at 05:06:10PM -0800, Ram Pai wrote: > On Thu, Jan 25, 2018 at 04:05:12PM +1100, Paul Mackerras wrote: > > POWER9 processors up to and including "Nimbus" v2.2 have hardware > > bugs relating to transactional memory and thread reconfiguration.

[RFC PATCH] powerpc/powernv: Provide a way to force a core into SMT4 mode

nnoticeable compared to the latency of going into and out of a stop state. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/paca.h | 3 ++ arch/powerpc/kernel/asm-offsets.c | 1 + arch/powerpc/kernel/idle_book3s.S | 15 + arch/powerpc/pla

Re: [PATCH 25/26] KVM: PPC: Book3S PR: Support TAR handling for PR KVM HTM.

On Thu, Jan 11, 2018 at 06:11:38PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > Currently guest kernel doesn't handle TAR fac unavailable and it always > runs with TAR bit on. PR KVM will lazily enable TAR. TAR is not a > frequent-use reg and it is not

Re: [PATCH 23/26] KVM: PPC: Book3S PR: add emulation for tabort. for privilege guest

On Thu, Jan 11, 2018 at 06:11:36PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > Currently privilege guest will be run with TM disabled. > > Although the privilege guest cannot initiate a new transaction, > it can use tabort to terminate its problem

Re: [PATCH 22/26] KVM: PPC: Book3S PR: add emulation for trechkpt in PR KVM.

On Thu, Jan 11, 2018 at 06:11:35PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > This patch adds host emulation when guest PR KVM executes "trechkpt.", > which is a privileged instruction and will trap into host. > > We firstly copy vcpu ongoing content

Re: [PATCH 21/26] KVM: PPC: Book3S PR: adds emulation for treclaim.

On Thu, Jan 11, 2018 at 06:11:34PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > This patch adds support for "treclaim." emulation when PR KVM guest > executes treclaim. and traps to host. > > We will firstly doing treclaim. and save TM checkpoint and

Re: [PATCH 20/26] KVM: PPC: Book3S PR: enable NV reg restore for reading TM SPR at guest privilege state

o it is necessary to restore NV GPRs at this > case, to reflect the update to NV RT. > > This patch make kvmppc_handle_fac() return GUEST_RESUME_NV at TM fac > exception and with guest privilege state. > > Signed-off-by: Simon Guo <wei.guo.si...@gmail.com> Reviewed-by: Paul Mackerras <pau...@ozlabs.org>

Re: [PATCH 19/26] KVM: PPC: Book3S PR: always fail transaction in guest privilege state

On Thu, Jan 11, 2018 at 06:11:32PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > Currently kernel doesn't use transaction memory. > And there is an issue for privilege guest that: > tbegin/tsuspend/tresume/tabort TM instructions can impact MSR TM bits >

Re: [PATCH 18/26] KVM: PPC: Book3S PR: make mtspr/mfspr emulation behavior based on active TM SPRs

On Thu, Jan 11, 2018 at 06:11:31PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > The mfspr/mtspr on TM SPRs(TEXASR/TFIAR/TFHAR) are non-privileged > instructions and can be executed at PR KVM guest without trapping > into host in problem state. We only

Re: [PATCH 17/26] KVM: PPC: Book3S PR: add math support for PR KVM HTM

On Thu, Jan 11, 2018 at 06:11:30PM +0800, wei.guo.si...@gmail.com wrote: > ines: 219 > > From: Simon Guo > > The math registers will be saved into vcpu->arch.fp/vr and corresponding > vcpu->arch.fp_tm/vr_tm area. > > We flush or giveup the math regs into

Re: [PATCH 00/26] KVM: PPC: Book3S PR: Transaction memory support on PR KVM

On Tue, Jan 23, 2018 at 04:38:32PM +1100, Paul Mackerras wrote: > On Thu, Jan 11, 2018 at 06:11:13PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > In current days, many OS distributions have utilized transaction > >

Re: [PATCH 00/26] KVM: PPC: Book3S PR: Transaction memory support on PR KVM

On Thu, Jan 11, 2018 at 06:11:13PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > In current days, many OS distributions have utilized transaction > memory functionality. In PowerPC, HV KVM supports TM. But PR KVM > does not. > > The drive for the

Re: [PATCH 07/26] KVM: PPC: Book3S PR: add TEXASR related macros

y: Simon Guo <wei.guo.si...@gmail.com> Reviewed-by: Paul Mackerras <pau...@ozlabs.org> This and some of your other patches will need to go via Michael Ellerman's tree. Paul.

Re: [PATCH 04/26] KVM: PPC: Book3S PR: add C function wrapper for _kvmppc_save/restore_tm()

On Thu, Jan 11, 2018 at 06:11:17PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > Currently _kvmppc_save/restore_tm() APIs can only be invoked from > assembly function. This patch adds C function wrappers for them so > that they can be safely called from C

Re: [PATCH 16/26] KVM: PPC: Book3S PR: add transaction memory save/restore skeleton for PR KVM

M status at kvmppc_restore_tm_pr(). To solve this > issue, we save current MSR into vcpu->arch.save_msr_tm at > kvmppc_save_tm_pr(), and kvmppc_restore_tm_pr() check TS bits of > vcpu->arch.save_msr_tm to decide whether to do TM restore. > > Signed-off-by: Simon Guo <wei.guo.si...@gmail.com>

Re: [PATCH 02/26] KVM: PPC: Book3S PR: add new parameter (guest MSR) for kvmppc_save_tm()/kvmppc_restore_tm()

On Thu, Jan 11, 2018 at 06:11:15PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > HV KVM and PR KVM need different MSR source to indicate whether > treclaim. or trecheckpoint. is necessary. > > This patch add new parameter (guest MSR) for these

Re: [PATCH 10/26] KVM: PPC: Book3S PR: set MSR HV bit accordingly for PPC970 and others.

atch set MSR HV=1 for G5 machines and HV=0 for others on PR > KVM guest. > > Signed-off-by: Simon Guo <wei.guo.si...@gmail.com> > Suggested-by: Paul Mackerras <pau...@ozlabs.org> Reviewed-by: Paul Mackerras <pau...@ozlabs.org>

Re: [PATCH 13/26] KVM: PPC: Book3S PR: adds new kvmppc_copyto_vcpu_tm/kvmppc_copyfrom_vcpu_tm API for PR KVM.

CPU area. > > PR KVM will use these APIs for treclaim. or trchkpt. emulation. > > Signed-off-by: Simon Guo <wei.guo.si...@gmail.com> > Reviewed-by: Paul Mackerras <pau...@ozlabs.org> Actually, I take that back. You have missed XER. :) Paul.

Re: [PATCH 3/6] KVM: PPC: Book3S HV: Allow HPT and radix on the same core for POWER9 v2.2

On Wed, Jan 17, 2018 at 10:14:45PM +1100, Benjamin Herrenschmidt wrote: > On Wed, 2018-01-17 at 20:51 +1100, Paul Mackerras wrote: > > + > > + /* > > +* POWER9 chips before version 2.02 can't have some threads in > > +* HPT mode and some in

[PATCH 6/6] KVM: PPC: Book3S HV: Work around transactional memory bugs in POWER9

treclaim instruction that had done failure recording, not the treclaim done in hypervisor state in the guest exit path. With this, the KVM_CAP_PPC_HTM capability returns true (1) even if transactional memory is not available to host userspace. Signed-off-by: Paul Mackerras <pau...@ozlabs.org>

[PATCH 5/6] powerpc: Add a CPU feature bit for TM bug workarounds on POWER9 v2.2

This adds a CPU feature bit which is set for POWER9 "Nimbus" DD2.2 processors which will be used to enable software emulation for some transactional memory instructions, in order to work around hardware bugs. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/pow

[PATCH 4/6] KVM: PPC: Book3S HV: Improve handling of debug-trigger HMIs on POWER9

This also removes a BUG_ON in the KVM code. BUG_ON is generally not useful in KVM guest entry/exit code since it is difficult to handle the resulting trap gracefully. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/hmi.h | 4 + arch/powerpc/i

[PATCH 2/6] KVM: PPC: Book3S HV: Do SLB load/unload with guest LPCR value loaded

to a new label 'guest_bypass' and we move the SLB unload code to before this label. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 109 1 file changed, 55 insertions(+), 54 deletions(-) diff --git a/arch/power

[PATCH 3/6] KVM: PPC: Book3S HV: Allow HPT and radix on the same core for POWER9 v2.2

ve to take steps to avoid having some threads in HPT mode and some in radix mode (so-called "mixed mode"). Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv.c | 28 ++-- 1 file changed, 22 insertions(+), 6 deletions(-) dif

[PATCH 0/6] KVM: PPC: Book3S HV: Changes for POWER9 v2.2 support

The POWER9 "Nimbus" v2.2 (referred to as DD2.2) chip has some hardware bugs fixed that were present in earlier versions, and contains new workarounds for other hardware bugs. POWER9 DD2.2 can run with some threads of a core in hashed page table (HPT) MMU mode while other threads are in radix MMU

[PATCH 1/6] KVM: PPC: Book3S HV: Make sure we don't re-enter guest without XIVE loaded

oller") Cc: sta...@vger.kernel.org # v4.11+ Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 40 - 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/

Re: [PATCH] KVM: PPC: Use seq_puts() in kvmppc_exit_timing_show()

On Sun, Jan 07, 2018 at 10:18:08AM +0100, SF Markus Elfring wrote: > From: Markus Elfring > Date: Sun, 7 Jan 2018 10:07:36 +0100 > > A headline should be quickly put into a sequence. Thus use the > function "seq_puts" instead of "seq_printf" for this purpose. > >

Re: [PATCH] KVM: PPC: Book3S HV: Remove vcpu->arch.dec usage

On Tue, Dec 19, 2017 at 03:56:24PM +0100, Alexander Graf wrote: > On Book3S in HV mode, we don't use the vcpu->arch.dec field at all. > Instead, all logic is built around vcpu->arch.dec_expires. > > So let's remove the one remaining piece of code that was setting it. > > Signed-off-by: Alexander

Re: [RFC PATCH kernel] KVM: PPC: Book3S PR: Fix WIMG handling under pHyp

On Wed, Nov 22, 2017 at 02:42:21PM +1100, Alexey Kardashevskiy wrote: > 96df226 "KVM: PPC: Book3S PR: Preserve storage control bits" added WIMG > bits preserving but it missed 2 special cases: > - a magic page in kvmppc_mmu_book3s_64_xlate() and > - guest real mode in kvmppc_handle_pagefault(). >

Re: [PATCH RESEND 1/1] KVM: PPC: Book3S: Add MMIO emulation for VMX instructions

On Mon, Jan 08, 2018 at 04:29:31PM -0200, Jose Ricardo Ziviani wrote: > This patch provides the MMIO load/store vector indexed > X-Form emulation. > > Instructions implemented: lvx, stvx > > Signed-off-by: Jose Ricardo Ziviani What testing has been done of this

Re: [PATCH] KVM: PPC: Book3S: Add capabilities for Meltdown/Spectre workarounds

On Tue, Jan 09, 2018 at 07:28:35PM +1100, Suraj Jitindar Singh wrote: [snip] > > + rc = plpar_get_cpu_characteristics(); > > + if (rc == H_SUCCESS) { > > + if (!(c.behavior & > > H_GET_CPU_CHAR_BEHAV_L1_FLUSH_LOW_PRIV)) > >

[PATCH v2] KVM: PPC: Book3S: Add capabilities for Meltdown/Spectre workarounds

that requires software changes is provided; the current hardware fix is to prevent speculation past indirect branches. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- Note: This patch depends on the patch "powerpc/pseries: Add H_GET_CPU_CHARACTERISTICS flags & wrapper" by Michael

[PATCH] KVM: PPC: Book3S: Add capabilities for Meltdown/Spectre workarounds

that requires software changes is provided; the current hardware fix is to prevent speculation past indirect branches. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- Note: This patch depends on the patch "powerpc/pseries: Add H_GET_CPU_CHARACTERISTICS flags & wrapper" by Michael

Re: [PATCH 03/11] powerpc/64s: Simple RFI macro conversions

On Mon, Jan 08, 2018 at 06:09:51PM +0100, Peter Zijlstra wrote: > On Tue, Jan 09, 2018 at 03:54:45AM +1100, Michael Ellerman wrote: > > diff --git a/arch/powerpc/kvm/book3s_rmhandlers.S > > b/arch/powerpc/kvm/book3s_rmhandlers.S > > index 42a4b237df5f..34a5adeff084 100644 > > ---

Re: [PATCH] KVM: PPC: Book3S: fix XIVE migration of pending interrupts

On Fri, Dec 22, 2017 at 03:34:20PM +1100, Michael Ellerman wrote: > Laurent Vivier writes: > > > On 12/12/2017 13:02, Cédric Le Goater wrote: > >> When restoring a pending interrupt, we are setting the Q bit to force > >> a retrigger in xive_finish_unmask(). But we also need

[RFC PATCH 0/2] KVM: PPC: Book3S HV: Transactional memory bug workarounds for POWER9

This series adds emulation for some transactional memory instructions that will be used on POWER9 DD2.2 processors as part of the workarounds for hardware bugs. The basic idea is that because the CPU hardware cannot maintain a full checkpoint of the architected state for all four threads, it

[RFC PATCH 2/2] KVM: PPC: Book3S HV: Work around transactional memory bugs in POWER9

treclaim instruction that had done failure recording, not the treclaim done in hypervisor state in the guest exit path. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/kvm_asm.h| 2 + arch/powerpc/include/asm/kvm_book3s.h | 4 + arch/powerpc/i

[RFC PATCH 1/2] powerpc: Add a CPU feature bit for TM bug workarounds on POWER9 DD2.2

This adds a CPU feature bit which is set for POWER9 DD2.2 processors which will be used to enable software emulation for some transactional memory instructions, in order to work around hardware bugs. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/cputable.

Re: [PATCH] powerpc/xive: store server for masked interrupt in kvmppc_xive_set_xive()

On Fri, Nov 24, 2017 at 07:38:13AM +1100, Benjamin Herrenschmidt wrote: > On Thu, 2017-11-23 at 10:06 +0100, Laurent Vivier wrote: > > This is needed to map kvmppc_xive_set_xive() behavior > > to kvmppc_xics_set_xive(). > > > > As we store the server, kvmppc_xive_get_xive() can return > > the

Re: [PATCH] KVM: PPC: Book3S HV: check for XIVE device before executing the XICS hcalls

On Mon, Nov 27, 2017 at 08:30:17AM +0100, Cédric Le Goater wrote: > When QEMU is started with the option kernel_irqchip=òff, the kvm XICS > hcalls are being used even though a kvm XICS device has not been > created on the host, resulting quickly in a failure and a broken > guest. > > The test

Re: [RFC PATCH] KVM: PPC: Book3S HV: Handle host system reset in guest mode

On Fri, Nov 03, 2017 at 03:38:03PM +1100, Nicholas Piggin wrote: > If the host takes a system reset interrupt while a guest is running, > the CPU must exit the guest before processing the host exception > handler. > > After this patch, taking a sysrq+x with a CPU running in a guest > gives a

Re: [PATCH 00/16] Remove hash page table slot tracking from linux PTE

On Sun, Oct 29, 2017 at 05:51:06PM -0700, Ram Pai wrote: > On Mon, Oct 30, 2017 at 09:04:17AM +1100, Paul Mackerras wrote: > > On Sat, Oct 28, 2017 at 03:35:32PM -0700, Ram Pai wrote: > > > > > > I like the idea of not tracking the slots at all. It is somet

Re: [PATCH 00/16] Remove hash page table slot tracking from linux PTE

On Sat, Oct 28, 2017 at 03:35:32PM -0700, Ram Pai wrote: > > I like the idea of not tracking the slots at all. It is something the > guest should not be knowing or tracking. Why do you say that? Paul.

Re: [PATCH 00/16] Remove hash page table slot tracking from linux PTE

On Fri, Oct 27, 2017 at 10:57:13AM +0530, Aneesh Kumar K.V wrote: > > > On 10/27/2017 10:04 AM, Paul Mackerras wrote: > >How do we interpret these numbers? Are they times, or speed? Is > >larger better or worse? > > Sorry for not including the details. They are

Re: [PATCH 00/16] Remove hash page table slot tracking from linux PTE

On Fri, Oct 27, 2017 at 09:38:17AM +0530, Aneesh Kumar K.V wrote: > Hi, > > With hash translation mode we always tracked the hash pte slot details in > linux page table. > This occupied space in the linux page table and also limitted our ability to > support > linux features that require

Re: [PATCH] powerpc: Fix check for copy/paste instructions in alignment handler

On Thu, Oct 26, 2017 at 01:22:37AM +1000, Nicholas Piggin wrote: > On Wed, 25 Oct 2017 18:16:53 +1100 > Paul Mackerras <pau...@ozlabs.org> wrote: > > > Commit 07d2a628bc00 ("powerpc/64s: Avoid cpabort in context switch > > when possible", 2017-06-09) ch

Re: [PATCH] bitmap: Fix optimization of bitmap_set/clear for big-endian machines

On Wed, Oct 25, 2017 at 07:39:48AM +, Matthew Wilcox wrote: > Hang on, don't tell me you found this by inspection. Are you not running the > bitmap testcase, enabled by CONFIG_TEST_BITMAP? Either that should be > producing an error, or there's a missing test case, or your inspection is >

[PATCH] powerpc: Fix check for copy/paste instructions in alignment handler

This fixes it by ANDing both sides of the comparison with the mask. Fixes: 07d2a628bc00 ("powerpc/64s: Avoid cpabort in context switch when possible") Reported-by: Markus Trippelsdorf <mar...@trippelsdorf.de> Signed-off-by: Paul Mackerras <pau...@ozlabs.org> ---

[PATCH] bitmap: Fix optimization of bitmap_set/clear for big-endian machines

turn bitmap_set and bitmap_clear into memset when possible") Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- This was found by inspection. I'm pretty sure commit 2c6deb01525a is wrong as well on big-endian machines. include/linux/bitmap.h | 14 ++ 1 file changed, 10

Re: [PATCH kernel] KVM: PPC: Enable in-kernel TCE handlers for PR KVM

On Wed, Oct 11, 2017 at 04:01:08PM +1100, Alexey Kardashevskiy wrote: > The handlers support PR KVM from the day one; however the PR KVM's > enable/disable hcalls handler missed these ones. > > Signed-off-by: Alexey Kardashevskiy Thanks, applied to my kvm-ppc-next branch. Paul.

Re: [PATCH] KVM: PPC: Book3S HV: Delete an error message for a failed memory allocation in kvmppc_allocate_hpt()

On Thu, Oct 05, 2017 at 01:23:30PM +0200, SF Markus Elfring wrote: > From: Markus Elfring > Date: Thu, 5 Oct 2017 13:16:51 +0200 > > Omit an extra message for a memory allocation failure in this function. > > This issue was detected by using the Coccinelle

Re: [PATCH 1/10] KVM: PPC: Book3S HV: Use ARRAY_SIZE macro

On Sun, Sep 03, 2017 at 02:19:31PM +0200, Thomas Meyer wrote: > Use ARRAY_SIZE macro, rather than explicitly coding some variant of it > yourself. > Found with: find -type f -name "*.c" -o -name "*.h" | xargs perl -p -i -e > 's/\bsizeof\s*\(\s*(\w+)\s*\)\s*\ /\s*sizeof\s*\(\s*\1\s*\[\s*0\s*\]\s*\)

Re: [PATCH 6/7] KVM: PPC: Cocci spatch "vma_pages"

On Thu, Sep 21, 2017 at 12:29:36AM +0200, Thomas Meyer wrote: > Use vma_pages function on vma object instead of explicit computation. > Found by coccinelle spatch "api/vma_pages.cocci" > > Signed-off-by: Thomas Meyer Thanks, applied to my kvm-ppc-next branch, with the headline

Re: [PATCH v2] KVM: PPC: Book3S PR: only install valid SLBs during KVM_SET_SREGS

On Mon, Oct 02, 2017 at 10:40:22AM +0200, Greg Kurz wrote: > Userland passes an array of 64 SLB descriptors to KVM_SET_SREGS, > some of which are valid (ie, SLB_ESID_V is set) and the rest are > likely all-zeroes (with QEMU at least). > > Each of them is then passed to

Re: [PATCH kernel] KVM: PPC: Protect kvmppc_gpa_to_ua() with srcu

On Wed, Oct 11, 2017 at 04:00:34PM +1100, Alexey Kardashevskiy wrote: > kvmppc_gpa_to_ua() accesses KVM memory slot array via > srcu_dereference_check() and this produces warnings from RCU like below. > > This extends the existing srcu_read_lock/unlock to cover that > kvmppc_gpa_to_ua() as well.

Re: [PATCH] KVM: PPC: Book3S HV: POWER9 more doorbell fixes

On Tue, Oct 10, 2017 at 08:18:28PM +1000, Nicholas Piggin wrote: > - Add another case where msgsync is required. > - Required barrier sequence for global doorbells is msgsync ; lwsync > - POWER9 DD1 has a different barrier sequence that we don't implement, > so remove > > When msgsnd is used

Re: [PATCH] KVM: PPC: fix oops when checking KVM_CAP_PPC_HTM

On Thu, Sep 14, 2017 at 11:56:25PM +0200, Greg Kurz wrote: > The following program causes a kernel oops: > > #include > #include > #include > #include > #include > > main() > { > int fd = open("/dev/kvm", O_RDWR); > ioctl(fd, KVM_CHECK_EXTENSION, KVM_CAP_PPC_HTM); > } > > This

Re: [PATCH] KVM: PPC: fix oops when checking KVM_CAP_PPC_HTM

On Fri, Oct 13, 2017 at 06:14:00PM +0200, Paolo Bonzini wrote: > On 13/10/2017 01:16, Greg Kurz wrote: > > Ping ? > > When is Paul back from vacation? :) Now. :) Paul.

Re: [PATCH v2 7/9] powerpc/64s: do not allocate lppaca if we are not virtualized

On Sun, Aug 13, 2017 at 11:33:44AM +1000, Nicholas Piggin wrote: > The "lppaca" is a structure registered with the hypervisor. This > is unnecessary when running on non-virtualised platforms. One field > from the lppaca (pmcregs_in_use) is also used by the host, so move > the host part out into

Re: [PATCH] KVM: PPC: Book3S PR: only call slbmte for valid SLB entries

On Tue, Sep 26, 2017 at 03:24:05PM +1000, Michael Ellerman wrote: > David Gibson writes: > > > On Fri, Sep 22, 2017 at 11:34:29AM +0200, Greg Kurz wrote: > >> Userland passes an array of 64 SLB descriptors to KVM_SET_SREGS, > >> some of which are valid (ie,

Possible bug in commit f3b3f28493d9

Commit f3b3f28493d9 ("powerpc/powernv/idle: Don't override default/deepest directly in kernel", 2017-03-22) made the following change in pnv_cpu_offline() in arch/powerpc/platforms/powernv/idle.c: - if (cpu_has_feature(CPU_FTR_ARCH_300)) { + if (cpu_has_feature(CPU_FTR_ARCH_300) &&

[PATCH] powerpc: Fix handling of alignment interrupt on dcbz instruction

("powerpc: Use instruction emulation infrastructure to handle alignment faults") Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kernel/align.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/

[PATCH] powerpc: Implement cross-endian emulation of larx and stcx instructions

interrupt handling, since these instructions cannot be emulated when the address is not aligned, because we have no way to do atomic unaligned accesses, in general. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/lib/sstep.c | 47 ++

[PATCH] powerpc: Fix kernel crash in emulation of vector loads and stores

rupt. It can be triggered using uprobes. Fixes: 350779a29f11 ("powerpc: Handle most loads and stores in instruction emulation code") Reported-by: Anton Blanchard <an...@ozlabs.org> Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/lib/ldstfp.S | 8 --

Re: [PATCH RFC] KVM: PPC: Book3S: Add MMIO emulation for VMX instructions

On Tue, Aug 29, 2017 at 07:18:02PM -0300, Jose Ricardo Ziviani wrote: > This patch provides the MMIO load/store vector indexed > X-Form emulation. > > Instructions implemented: lvx, stvx > > Signed-off-by: Jose Ricardo Ziviani Thanks for the patch. The basic outline

[PATCH 19/17] powerpc: Wrap register number correctly for string load/store instructions

rpc: Implement emulation of string loads and stores") Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/lib/sstep.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c index 2f6897c..c406611 100644 --- a

Re: [PATCH] KVM: PPC: Book3S HV: Fix invalid use of register expression

On Tue, Aug 15, 2017 at 02:37:01PM +1000, Michael Ellerman wrote: > From: Andreas Schwab > > binutils >= 2.26 now warns about misuse of register expressions in > assembler operands that are actually literals. In this instance r0 is > being used where a literal 0 should be

Re: [PATCH v2 1/9] KVM: PPC: Book3S HV: Fix H_REGISTER_VPA VPA size validation

On Sun, Aug 13, 2017 at 11:33:38AM +1000, Nicholas Piggin wrote: > KVM currently validates the size of the VPA registered by the client > against sizeof(struct lppaca), however we align (and therefore size) > that struct to 1kB to avoid crossing a 4kB boundary in the client. > > PAPR calls for

Re: [PATCH 1/2] KVM: PPC: e500: fix some NULL dereferences on error

On Thu, Jul 13, 2017 at 10:38:29AM +0300, Dan Carpenter wrote: > There are some error paths in kvmppc_core_vcpu_create_e500() where we > forget to set the error code. It means that we return ERR_PTR(0) which > is NULL and it results in a NULL pointer dereference in the caller. > > Signed-off-by:

Re: [PATCH RFC] powerpc: Implements MMIO emulation for lvx/stvx instructions

On Tue, Aug 29, 2017 at 07:18:01PM -0300, Jose Ricardo Ziviani wrote: > Hello! > > This patch implements MMIO emulation for two instructions: lvx and stvx. I > started to implement other instructions but I'd like to have this reviewed > beforehand because this is my first patch here and I'll

[PATCH v3 18/17] powerpc: Emulate load/store floating point as integer word instructions

This adds emulation for the lfiwax, lfiwzx and stfiwx instructions. This necessitated adding a new flag to indicate whether a floating point or an integer conversion was needed for LOAD_FP and STORE_FP, so this moves the size field in op->type up 4 bits. Signed-off-by: Paul Mackerras &

[PATCH v3 17/17] powerpc: Use instruction emulation infrastructure to handle alignment faults

. With this, we now need to include the instruction emulation code unconditionally. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/Kconfig| 4 - arch/powerpc/kernel/align.c | 774 ++-- arch/powerpc/lib/Makefile | 4 +- 3

[PATCH v3 16/17] powerpc: Separate out load/store emulation into its own function

This moves the parts of emulate_step() that deal with emulating load and store instructions into a new function called emulate_loadstore(). This is to make it possible to reuse this code in the alignment handler. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/inclu

[PATCH v3 15/17] powerpc: Handle opposite-endian processes in emulation code

32-bit 603, 604, 740/750, 74xx CPUs. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/sstep.h | 7 +- arch/powerpc/lib/sstep.c | 184 +++ 2 files changed, 131 insertions(+), 60 deletions(-) diff --git a/arch/powerpc/

[PATCH v3 14/17] powerpc: Set regs->dar if memory access fails in emulate_step()

ond page. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/lib/sstep.c | 74 ++-- 1 file changed, 52 insertions(+), 22 deletions(-) diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c index fa20f3a..5c0f50b 100644 -

[PATCH v3 13/17] powerpc: Emulate the dcbz instruction

it will be needed in that situation.) Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/sstep.h | 2 ++ arch/powerpc/lib/sstep.c | 32 2 files changed, 34 insertions(+) diff --git a/arch/powerpc/include/asm/sstep.h b/arch/p

[PATCH v3 12/17] powerpc: Emulate load/store floating double pair instructions

This adds lfdp[x] and stfdp[x] to the set of instructions that analyse_instr() and emulate_step() understand. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/lib/sstep.c | 68 1 file changed, 52 insertions(+), 16 del

[PATCH v3 11/17] powerpc: Emulate vector element load/store instructions

This adds code to analyse_instr() and emulate_step() to handle the vector element loads and stores: lvebx, lvehx, lvewx, stvebx, stvehx, stvewx. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/lib/sstep.c | 38 -- 1 file chang

[PATCH v3 10/17] powerpc: Emulate FP/vector/VSX loads/stores correctly when regs not live

to emulate the instruction. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/sstep.h | 1 + arch/powerpc/lib/ldstfp.S| 241 +++ arch/powerpc/lib/sstep.c | 228 +--- 3 files change

[PATCH v3 09/17] powerpc: Make load/store emulation use larger memory accesses

these new functions. These new functions also simplify the code in do_fp_load() and do_fp_store() for the unaligned cases. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/lib/sstep.c | 235 +-- 1 file changed, 106 insertions(+

[PATCH v3 08/17] powerpc: Add emulation for the addpcis instruction

is placed on an addpcis instruction. This fixes the problem by adding emulation of it to analyse_instr(). Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/lib/sstep.c | 14 +++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/lib/sst

[PATCH v3 07/17] powerpc: Don't update CR0 in emulation of popcnt, prty, bpermd instructions

The architecture shows the least-significant bit of the instruction word as reserved for the popcnt[bwd], prty[wd] and bpermd instructions, that is, these instructions never update CR0. Therefore this changes the emulation of these instructions to skip the CR0 update. Signed-off-by: Paul

[PATCH v3 06/17] powerpc: Fix emulation of the isel instruction

Fixes: e27f71e5ff3c ("powerpc/lib/sstep: Add isel instruction emulation") Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/lib/sstep.c | 18 ++ 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/s

[PATCH v3 05/17] powerpc/64: Fix update forms of loads and stores to write 64-bit EA

code writes the truncated address to the RA register. This fixes it by keeping the full 64-bit EA in the instruction_op structure, truncating the address in emulate_step() where it is used to address memory, rather than in the address computations in analyse_instr(). Signed-off-by: Paul Mackerras

[PATCH v3 04/17] powerpc: Handle most loads and stores in instruction emulation code

of the architecture, and their opcodes have been reused for other instructions in POWER9 (lxvb16x and stxvb16x). The emulation for the VSX loads and stores uses helper functions which don't access registers or memory directly, which can hopefully be reused by KVM later. Signed-off-by: Paul Mackerras <

[PATCH v3 01/17] powerpc: Correct instruction code for xxlor instruction

a VSX load or store from any register other than vsr0, the bitwise complement of the correct value will be loaded or stored. This corrects the error. Fixes: 0016a4cf5582 ("powerpc: Emulate most Book I instructions in emulate_step()") Signed-off-by: Paul Mackerras <pau...@ozlabs.org> ---

[PATCH v3 00/17] powerpc: Do alignment fixups using analyse_instr etc.

This series extends the instruction emulation infrastructure in arch/powerpc/lib/sstep.c and uses it for emulating instructions when we get an alignment interrupt. The advantage of this is that we only have to add the new POWER9 instructions in one place, and it fixes several bugs in alignment

[PATCH v3 03/17] powerpc: Don't check MSR FP/VMX/VSX enable bits in analyse_instr()

/VSX enable bits in the MSR image in the pt_regs are zero. Since analyse_instr() doesn't make any changes to register state, it is reasonable for it to indicate what the effect of an instruction would be even though the relevant enable bit is off. Signed-off-by: Paul Mackerras <pau...@ozlabs.

[PATCH v3 02/17] powerpc: Change analyse_instr so it doesn't modify *regs

() can then use that information to update a pt_regs struct appropriately. As a minor cleanup, this replaces inline asm using the cntlzw and cntlzd instructions with calls to __builtin_clz() and __builtin_clzl(). Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/s

Re: [PATCH v3 4/4] powerpc/64s: idle ESL=0 stop can avoid MSR and save/restore overhead

g has to be saved. The following > + * instructions up to the blr must be skipped if we want to > + * use power_enter_stop_kvm_rm. > + */ > + andis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED I realize you're just moving existing code, but I think this would be clearer (to me, anyway) as andis. r4, r3, (PSSCR_EC | PSSCR_ESL)@h Apart from that very minor nit, Reviewed-by: Paul Mackerras <pau...@ozlabs.org>

Re: [PATCH v3 2/4] powerpc/64s: idle POWER9 can execute stop without a sync sequence

On Fri, Aug 25, 2017 at 02:30:34PM +1000, Nicholas Piggin wrote: > Reviewed-by: Gautham R. Shenoy > Signed-off-by: Nicholas Piggin > --- > arch/powerpc/include/asm/cpuidle.h | 16 > arch/powerpc/kernel/idle_book3s.S | 26

Re: [PATCH v3 3/4] powerpc/64s: idle POWER9 can execute stop in virtual mode

WER9 does not require real mode to stop, and presently does not > + * set hwthread_state for KVM (threads don't share MMU context), so > + * we can remain in virtual mode for this. > + */ > + bctr > +END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) > /* > +

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