Re: [PATCH v3 1/4] KVM: PPC: Book3S HV: POWER9 does not require secondary thread management

las Piggin <npig...@gmail.com> Some of the feature sections seem a little unnecessary except for documentation purposes (e.g. the second one added after the kvm_no_guest label), but they won't actually hurt, so: Acked-by: Paul Mackerras <pau...@ozlabs.org>

Re: Re: [PATCH] fix memory leak on kvm_vm_ioctl_create_spapr_tce

On Mon, Aug 28, 2017 at 06:28:08AM +0100, Al Viro wrote: > On Mon, Aug 28, 2017 at 02:38:37PM +1000, Paul Mackerras wrote: > > On Sun, Aug 27, 2017 at 10:02:20PM +0100, Al Viro wrote: > > > On Wed, Aug 23, 2017 at 04:06:24PM +1000, Paul Mackerras wrote: > > > > >

Re: Re: [PATCH] fix memory leak on kvm_vm_ioctl_create_spapr_tce

On Sun, Aug 27, 2017 at 10:02:20PM +0100, Al Viro wrote: > On Wed, Aug 23, 2017 at 04:06:24PM +1000, Paul Mackerras wrote: > > > It seems to me that it would be better to do the anon_inode_getfd() > > call before the kvm_get_kvm() call, and go to the fail label if it > &

[PATCH] KVM: PPC: Book3S HV: Protect updates to spapr_tce_tables list

ally. So, in each case there is no harmful effect. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_64_vio.c | 21 ++--- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/arch/powerpc/kvm/book3s_64_vio.c b/arch/powerpc/kvm/book3s

[PATCH v2 09/10] powerpc: Handle opposite-endian processes in emulation code

/write_mem with a byte count that was not 1, 2, 4 or 8. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/sstep.h | 4 +- arch/powerpc/lib/sstep.c | 202 ++- 2 files changed, 135 insertions(+), 71 deletions(-) diff --git

[PATCH v2 10/10] powerpc/64: Fix update forms of loads and stores to write 64-bit EA

code writes the truncated address to the RA register. This fixes it by keeping the full 64-bit EA in the instruction_op structure, truncating the address in emulate_step() where it is used to address memory, rather than in the address computations in analyse_instr(). Signed-off-by: Paul Mackerras

[PATCH v2 08/10] powerpc: Emulate load/store floating double pair instructions

This adds lfdp[x] and stfdp[x] to the set of instructions that analyse_instr() and emulate_step() understand. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/lib/sstep.c | 76 ++-- 1 file changed, 60 insertions(+), 16 del

[PATCH v2 07/10] powerpc: Handle vector element load/stores in emulation code

This adds code to analyse_instr() and emulate_step() to handle the vector element loads and stores: lvebx, lvehx, lvewx, stvebx, stvehx, stvewx. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/lib/sstep.c | 50 ++-- 1 file c

[PATCH v2 06/10] powerpc: Emulate FP/vector/VSX loads/stores correctly when regs not live

to a local variable, then reenables preemption and then copies the register image to memory. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/sstep.h | 1 + arch/powerpc/lib/ldstfp.S| 241 +++ arch/powerpc/lib/s

[PATCH v2 05/10] powerpc: Make load/store emulation use larger memory accesses

these new functions. These new function also simplify the code in do_fp_load() and do_fp_store() for the unaligned cases. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/lib/sstep.c | 237 +-- 1 file changed, 106 insertions(+), 131 del

[PATCH v2 04/10] powerpc: Add emulation for the addpcis instruction

is placed on an addpcis instruction. This fixes the problem by adding emulation of it to analyse_instr(). Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/lib/sstep.c | 14 +++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/lib/sst

[PATCH v2 03/10] powerpc: Fix emulation of the isel instruction

eld, which indicates which CR bit to use to select the result. Therefore, for the isel emulation to work correctly when BC != 0, we need to match on ((instr >> 1) & 0x1f) == 15). To do this, we pull the isel case out of the switch statement and put it in an if statement of its own.

[PATCH v2 02/10] powerpc: Change analyse_instr so it doesn't modify *regs

() can then use that information to update a pt_regs struct appropriately. As a minor cleanup, this replaces inline asm using the cntlzw and cntlzd instructions with calls to __builtin_clz() and __builtin_clzl(). Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/s

[PATCH v2 01/10] powerpc: Handle most loads and stores in instruction emulation code

of the architecture, and their opcodes have been reused for other instructions in POWER9 (lxvb16x and stxvb16x). The emulation for the VSX loads and stores uses helper functions which don't access registers or memory directly, which can hopefully be reused by KVM later. Signed-off-by: Paul Mackerras <

[PATCH v2 0/10] powerpc: Beef up single-stepping/instruction emulation infrastructure

This patch series extends the code in arch/powerpc/lib/sstep.c so that it handles almost all load and store instructions -- all except the atomic memory operations (lwat, stwat, etc.). It also makes sure that we use the largest possible aligned accesses to access memory and that we don't access

Re: [PATCH v2 12/14] KVM: PPC: Book3S HV: POWER9 can execute stop without a sync sequence

On Sat, Aug 12, 2017 at 02:39:10AM +1000, Nicholas Piggin wrote: > Reviewed-by: Gautham R. Shenoy > Signed-off-by: Nicholas Piggin > --- > arch/powerpc/kvm/book3s_hv_rmhandlers.S | 24 > 1 file changed, 12 insertions(+), 12

Re: [PATCH v2 10/14] KVM: PPC: Book3S HV: POWER9 does not require secondary thread management

On Sat, Aug 12, 2017 at 02:39:08AM +1000, Nicholas Piggin wrote: > POWER9 CPUs have independent MMU contexts per thread, so KVM does not > need to quiesce secondary threads, so the hwthread_req/hwthread_state > protocol does not have to be used. So patch it away on POWER9, and patch > away the

Re: [PATCH v2] KVM: PPC: Book3S: Fix race and leak in kvm_vm_ioctl_create_spapr_tce()

On Thu, Aug 24, 2017 at 07:11:38PM +1000, Paul Mackerras wrote: Ignore this. My apologies. Paul.

[PATCH really v2] KVM: PPC: Book3S: Fix race and leak in kvm_vm_ioctl_create_spapr_tce()

he new entry to the list. Finally, on failure we now call kvmppc_account_memlimit to decrement the process's count of locked memory pages. Reported-by: Nixiaoming <nixiaom...@huawei.com> Reported-by: David Hildenbrand <da...@redhat.com> Signed-off-by: Paul Mackerras <pau...@ozla

[PATCH v2] KVM: PPC: Book3S: Fix race and leak in kvm_vm_ioctl_create_spapr_tce()

he new entry to the list. Finally, on failure we now call kvmppc_account_memlimit to decrement the process's count of locked memory pages. Reported-by: Nixiaoming <nixiaom...@huawei.com> Reported-by: David Hildenbrand <da...@redhat.com> Signed-off-by: Paul Mackerras <pau...@ozla

Re: [PATCH] KVM: PPC: Book3S: Fix race and leak in kvm_vm_ioctl_create_spapr_tce()

On Thu, Aug 24, 2017 at 06:43:22AM +, Nixiaoming wrote: > >From: Paul Mackerras [mailto:pau...@ozlabs.org] Thursday, August 24, 2017 > >11:40 AM > > > >Nixiaoming pointed out that there is a memory leak in > >kvm_vm_ioctl_create_spapr_tce() if the ca

[PATCH] KVM: PPC: Book3S: Fix race and leak in kvm_vm_ioctl_create_spapr_tce()

he new entry to the list. Finally, on failure we now call kvmppc_account_memlimit to decrement the process's count of locked memory pages. Reported-by: Nixiaoming <nixiaom...@huawei.com> Reported-by: David Hildenbrand <da...@redhat.com> Signed-off-by: Paul Mackerras <pau...@ozlabs.o

Re: Re: [PATCH] fix memory leak on kvm_vm_ioctl_create_spapr_tce

On Wed, Aug 23, 2017 at 01:43:08AM +, Nixiaoming wrote: > >On 22.08.2017 17:15, David Hildenbrand wrote: > >> On 22.08.2017 16:28, nixiaoming wrote: > >>> miss kfree(stt) when anon_inode_getfd return fail so add check > >>> anon_inode_getfd return val, and kfree stt > >>> > >>> Signed-off-by:

[PATCH RFC 7/7] powerpc: Handle opposite-endian processes in emulation code

This adds code to the load and store emulation code to byte-swap the data appropriately when the process being emulated is set to the opposite endianness to that of the kernel. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/sstep.h | 4 +- arch/power

[PATCH RFC 6/7] powerpc: Emulate load/store floating double pair instructions

This adds lfdp[x] and stfdp[x] to the set of instructions that analyse_instr() and emulate_step() understand. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/lib/sstep.c | 76 ++-- 1 file changed, 60 insertions(+), 16 del

[PATCH RFC 5/7] powerpc: Handle vector element load/stores in emulation code

This adds code to analyse_instr() and emulate_step() to handle the vector element loads and stores: lvebx, lvehx, lvewx, stvebx, stvehx, stvewx. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/lib/sstep.c | 50 ++-- 1 file c

[PATCH RFC 4/7] powerpc: Emulate FP/vector/VSX loads/stores correctly when regs not live

to a local variable, then reenables preemption and then copies the register image to memory. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/sstep.h | 1 + arch/powerpc/lib/ldstfp.S| 241 +++ arch/powerpc/lib/s

[PATCH RFC 3/7] powerpc: Make load/store emulation use larger memory accesses

these new functions. These new function also simplify the code in do_fp_load() and do_fp_store() for the unaligned cases. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/lib/sstep.c | 237 +-- 1 file changed, 106 insertions(+), 131 del

[PATCH RFC 2/7] powerpc: Change analyse_instr so it doesn't modify *regs

() can then use that information to update a pt_regs struct appropriately. As a minor cleanup, this replaces inline asm using the cntlzw and cntlzd instructions with calls to __builtin_clz() and __builtin_clzl(). Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/s

[PATCH RFC 1/7] powerpc: Extend instruction emulation infrastructure

of the architecture, and their opcodes have been reused for other instructions in POWER9 (lxvb16x and stxvb16x). The emulation for the VSX loads and stores uses helper functions which don't access registers or memory directly, which can hopefully be reused by KVM later. Signed-off-by: Paul Mackerras <

[PATCH RFC 0/7] powerpc: Beef up single-stepping/instruction emulation infrastructure

This patch series extends the code in arch/powerpc/lib/sstep.c so that it handles almost all load and store instructions -- all except the atomic memory operations (lwat, stwat, etc.). It also makes sure that we use the largest possible aligned accesses to access memory and that we don't access

Re: [PATCH 1/2] KVM: PPC: e500: fix some NULL dereferences on error

On Thu, Jul 13, 2017 at 10:38:29AM +0300, Dan Carpenter wrote: > There are some error paths in kvmppc_core_vcpu_create_e500() where we > forget to set the error code. It means that we return ERR_PTR(0) which > is NULL and it results in a NULL pointer dereference in the caller. > > Signed-off-by:

Re: [PATCH v4] powerpc/mm/radix: Workaround prefetch issue with KVM

On Thu, Jul 20, 2017 at 05:36:56PM +1000, Benjamin Herrenschmidt wrote: > There's a somewhat architectural issue with Radix MMU and KVM. > > When coming out of a guest with AIL (ie, MMU enabled), we start > executing hypervisor code with the PID register still containing > whatever the guest has

Re: KVM guests freeze under upstream kernel

On Thu, Jul 20, 2017 at 12:02:23AM -0300, jos...@linux.vnet.ibm.com wrote: > On Thu, Jul 20, 2017 at 09:42:50AM +1000, Benjamin Herrenschmidt wrote: > > On Wed, 2017-07-19 at 16:46 -0300, jos...@linux.vnet.ibm.com wrote: > > > Hello! > > > > > > We're not able to boot any KVM guest using upstream

Re: [PATCH] powerpc/mm/radix: GR field got removed in ISA 3.0B

On Wed, Jun 21, 2017 at 10:50:12AM +0530, Aneesh Kumar K.V wrote: > The bit position is now marked reserved. Hence don't set the bit to 1. > > Signed-off-by: Aneesh Kumar K.V > --- > arch/powerpc/include/asm/book3s/64/mmu.h | 1 - > arch/powerpc/kvm/book3s_hv.c

[PATCH V3 0/2] KVM: PPC: Book3S HV: Support POWER9's large decrementer mode

One of the new features of POWER9 is that the decrementer (the facility that provides an interrupt after a programmable length of time) has been increased in size from 32 bits to 56 bits, allowing time intervals of up to about 814 days, compared to 4 seconds previously. This patch series adds

[PATCH V3 2/2] KVM: PPC: Book3S HV: Enable guests to use large decrementer mode on POWER9

the LPCR_LD bit in the guest LPCR value, and if it is set, omit the 32-bit sign extension that would otherwise be done. This doesn't change the DEC emulation used by PR KVM because PR KVM is not supported on POWER9 yet. This is partly based on an earlier patch by Oliver O'Halloran. Signed-off-by: Paul

[PATCH V3 1/2] KVM: PPC: Book3S HV: Cope with host using large decrementer mode

-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv_interrupts.S | 12 +++- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 23 +-- 2 files changed, 28 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/kvm/book3s_hv_interrupts.S b/arch/power

[PATCH V2 1/2] KVM: PPC: Book3S HV: Cope with host using large decrementer mode

large decrementer mode whenever it is set (even if firmware tells us that the large decrementer mode only gives us 32 bits) so that we get the sign extension in hardware. This is partly based on an earlier patch by Oliver O'Halloran. Cc: sta...@vger.kernel.org # v4.10+ Signed-off-by: Paul Mackerras

[PATCH V2 0/2] KVM: PPC: Book3S HV: Support POWER9's large decrementer mode

One of the new features of POWER9 is that the decrementer (the facility that provides an interrupt after a programmable length of time) has been increased in size from 32 bits to 56 bits, allowing time intervals of up to about 814 days, compared to 4 seconds previously. This patch series adds

[PATCH V2 2/2] KVM: PPC: Book3S HV: Enable guests to use large decrementer mode on POWER9

value, and if it is set, omit the 32-bit sign extension that would otherwise be done. This doesn't change the DEC emulation used by PR KVM because PR KVM is not supported on POWER9 yet. This is partly based on an earlier patch by Oliver O'Halloran. Signed-off-by: Paul Mackerras <pau...@ozlabs.

[PATCH] powerpc: Convert VDSO update function to use new update_vsyscall interface

8-bit arithmetic.) Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/Kconfig | 2 +- arch/powerpc/kernel/time.c | 68 +++--- 2 files changed, 53 insertions(+), 17 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig

[PATCH 1/2] KVM: PPC: Book3S HV: Cope with host using large decrementer mode

...@vger.kernel.org # v4.10+ Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/cputable.h | 4 +++- arch/powerpc/kernel/prom.c | 1 + arch/powerpc/kernel/time.c | 7 ++- arch/powerpc/kvm/book3s_hv_interrupts.S | 2 ++ arch/power

[PATCH 2/2] KVM: PPC: Book3S HV: Enable guests to use large decrementer mode on POWER9

value, and if it is set, omit the 32-bit sign extension that would otherwise be done. This doesn't change the DEC emulation used by PR KVM because PR KVM is not supported on POWER9 yet. This is partly based on an earlier patch by Oliver O'Halloran. Signed-off-by: Paul Mackerras <pau...@ozlabs.

[PATCH 0/2] KVM: PPC: Book3S HV: Support POWER9's large decrementer mode

One of the new features of POWER9 is that the decrementer (the facility that provides an interrupt after a programmable length of time) has been increased in size from 32 bits to 56 bits, allowing time intervals of up to about 814 days, compared to 4 seconds previously. This patch series adds

Re: [PATCH] powerpc/mm: Fix virt_addr_valid() etc. on 64-bit hash

; another solution, this commit does the minimal fix to make virt_addr_valid() > work, by explicitly checking that the address is in the linear mapping region. > > Fixes: bdbc29c19b26 ("powerpc: Work around gcc miscompilation of __pa() on > 64-bit") > Signed-off-by: Michael Ellerman <m...@ellerman.id.au> Reviewed-by: Paul Mackerras <pau...@ozlabs.org>

Re: P.A. Semi: "PR" KVM configure error after KVM changes for 4.12

On Tue, May 09, 2017 at 10:42:51AM +0200, Christian Zigotzky wrote: > Hi All, > > After the first batch of KVM changes for 4.12 merge window I get the > following error message if I want to configure the Linux kernel with KVM PR > support on my P.A. Semi board. > > warning: (KVM_BOOK3S_64)

Re: [RFC PATCH 4.8] powerpc/slb: Force a full SLB flush when we insert for a bad EA

a kernel address, so slb_finish_load() skips > + * trying to insert it into the SLB cache. > + */ > + li r9,SLB_CACHE_ENTRIES + 1 > + sth r9,PACASLBCACHEPTR(r13) > + crset 4*cr7+eq > li r10,0 /* BAD_VSID */ > li r9,0/* BAD_VSID */ > li r11,SLB_VSID_USER /* flags don't much matter */ > -- > 2.7.4 Looks reasonable. Reviewed-by: Paul Mackerras <pau...@ozlabs.org>

Re: [PATCH v3] KVM: PPC: Book3S HV: Native usage of the XIVE interrupt controller

To get this to compile for all my test configs takes this additional patch. I test-build configs with PR KVM and not HV (both modular and built-in) and a config with HV enabled but CONFIG_KVM_XICS=n. Please squash this into your topic branch. Paul. diff --git a/arch/powerpc/kvm/Kconfig

Re: [PATCH v3] KVM: PPC: Book3S HV: Native usage of the XIVE interrupt controller

On Wed, Apr 26, 2017 at 12:07:30PM +1000, Michael Ellerman wrote: > From: Benjamin Herrenschmidt > > This patch makes KVM capable of using the XIVE interrupt controller > to provide the standard PAPR "XICS" style hypercalls. It is necessary > for proper operations when

Re: [PATCH v3] KVM: PPC: Book3S PR: Do not fail emulation with mtspr/mfspr for unknown SPRs

On Tue, Apr 25, 2017 at 09:14:01AM +0200, Thomas Huth wrote: > On 05.04.2017 15:58, Thomas Huth wrote: > > According to the PowerISA 2.07, mtspr and mfspr should not always > > generate an illegal instruction exception when being used with an > > undefined SPR, but rather treat the instruction as

Re: [PATCH v2] KVM: PPC: Book3S PR: Do not fail emulation with mtspr/mfspr for unknown SPRs

On Tue, Apr 04, 2017 at 12:05:03PM +0200, Thomas Huth wrote: > According to the PowerISA 2.07, mtspr and mfspr should not always > generate an illegal instruction exception when being used with an > undefined SPR, but rather treat the instruction as a NOP or inject a > privilege exception in some

Re: [PATCH] KVM: PPC: Book3S PR: Do not fail emulation with mtspr/mfspr for unknown SPRs

On Mon, Apr 03, 2017 at 01:23:15PM +0200, Thomas Huth wrote: > According to the PowerISA 2.07, mtspr and mfspr should not generate > an illegal instruction exception when being used with an undefined SPR, > but rather treat the instruction as a NOP, inject a privilege exception > or an emulation

Re: [PATCH] KVM: PPC: Book3S PR: Do not always inject facility unavailable exceptions

On Mon, Apr 03, 2017 at 01:28:34PM +0200, Thomas Huth wrote: > KVM should not inject a facility unavailable exception into the guest > when it tries to execute a mtspr/mfspr instruction for an SPR that > is unavailable, and the vCPU is *not* running in PRoblem state. > > It's right that we inject

[PATCH] powerpc: Don't try to fix up misaligned load-with-reservation instructions

, this adds code to detect the l[hwdq]arx instructions and return without fixing them up, resulting in a SIGBUS being delivered to the process. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kernel/align.c | 27 +++ 1 file changed, 19 insertions

Re: [PATCH v4 2/3] powerpc/xmon: drop the nobt option from xmon plus minor fixes

On Wed, Mar 22, 2017 at 04:27:50PM -0300, Guilherme G. Piccoli wrote: > The xmon parameter nobt was added long time ago, by commit 26c8af5f01df > ("[POWERPC] print backtrace when entering xmon"). The problem that time > was that during a crash in a machine with USB keyboard, xmon wouldn't >

Re: [PATCH] kvm: powerpc: book3s: Disable preemption while accessing paca xics_phys filed

On Wed, Mar 29, 2017 at 12:07:03PM +1100, Michael Ellerman wrote: > Denis Kirjanov writes: > [...] > > @@ -3930,7 +3934,11 @@ static int kvmppc_book3s_init_hv(void) > > * indirectly, via OPAL. > > */ > > #ifdef CONFIG_SMP > > - if

Re: [PATCH V5 02/17] powerpc/mm/slice: Update the function prototype

On Wed, Mar 22, 2017 at 09:06:48AM +0530, Aneesh Kumar K.V wrote: > This avoid copying the slice_mask struct as function return value Did you do before/after comparisons of kernel text size? Paul.

Re: [PATCH V5 01/17] powerpc/mm/slice: Convert slice_mask high slice to a bitmap

On Wed, Mar 22, 2017 at 09:06:47AM +0530, Aneesh Kumar K.V wrote: > In followup patch we want to increase the va range which will result > in us requiring high_slices to have more than 64 bits. To enable this > convert high_slices to bitmap. We keep the number bits same in this patch > and later

Re: [PATCH V3 09/10] powerpc/mm: Lower the max real address to 53 bits

ng hash linux page table > specific bits to top of RPN field free up the software bits for other purpose. > > Signed-off-by: Aneesh Kumar K.V <aneesh.ku...@linux.vnet.ibm.com> Reviewed-by: Paul Mackerras <pau...@ozlabs.org>

Re: [PATCH V3 10/10] powerpc/mm: Move hash specific pte bits to be top bits of RPN

On Tue, Mar 21, 2017 at 11:00:00PM +0530, Aneesh Kumar K.V wrote: > We don't support the full 57 bits of physical address and hence can overload > the top bits of RPN as hash specific pte bits. > > Signed-off-by: Aneesh Kumar K.V <aneesh.ku...@linux.vnet.ibm.com> Reviewed-by: P

Re: [PATCH 12/12] powerpc/kvm: Native usage of the XIVE interrupt controller

On Mon, Mar 20, 2017 at 05:49:14PM +1100, Benjamin Herrenschmidt wrote: > This patch makes KVM capable of using the XIVE interrupt controller > to provide the standard PAPR "XICS" style hypercalls. It is necessary > for proper operations when the host uses XIVE natively. > > This has been lightly

Re: [PATCH kernel v11 00/10] powerpc/kvm/vfio: Enable in-kernel acceleration

On Wed, Mar 22, 2017 at 03:21:46PM +1100, Alexey Kardashevskiy wrote: > This is my current queue of patches to add acceleration of TCE > updates in KVM. > > This is based on sha1 093b995e3b55 Huang Ying "mm, swap: Remove > WARN_ON_ONCE() in free_swap_slot()". > > Please comment. Thanks. Looks

Re: kvmppc: BUG: using smp_processor_id() in preemptible

On Sat, Mar 25, 2017 at 03:00:27PM +0300, Denis Kirjanov wrote: > [Now with the proper subject] > > Hi, > > the commit 5a319350a46572d073042a3194676099dd2c135d > has introduces the following warning with CONFIG_DEBUG_PREEMPT enabled: > > [ 129.314426] BUG: using smp_processor_id() in

Re: [PATCH 06/12] powerpc/xive: Native exploitation of the XIVE interrupt controller

On Mon, Mar 20, 2017 at 05:49:08PM +1100, Benjamin Herrenschmidt wrote: > The XIVE interrupt controller is the new interrupt controller > found in POWER9. It supports advanced virtualization capabilities > among other things. > > Currently we use a set of firmware calls that simulate the old >

[PATCH 5/5] KVM: PPC: Add MMIO emulation for remaining floating-point instructions

For completeness, this adds emulation of the lfiwax and lfiwzx instructions. With this, all floating-point load and store instructions as of Power ISA V2.07 are emulated. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/ppc-opcode.h | 2 ++ arch/power

[PATCH 4/5] KVM: PPC: Emulation for more integer loads and stores

are emulated, except for those that are permitted to trap when used on cache-inhibited or write-through mappings (and which do in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx, lq/stq, and l[bhwdq]arx/st[bhwdq]cx. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/p

[PATCH 2/5] KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions

[pau...@ozlabs.org - some cleanups, fixes and rework, make it compile for Book E] Signed-off-by: Bin Lu <lbl...@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/disassemble.h | 5 + arch/powerpc/include/asm/kvm_host.h| 23 +++

[PATCH 3/5] KVM: PPC: Add MMIO emulation for stdx (store doubleword indexed)

u> Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/ppc-opcode.h | 1 + arch/powerpc/kvm/emulate_loadstore.c | 6 ++ 2 files changed, 7 insertions(+) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 1e37c

[PATCH 1/5] KVM: PPC: Provide functions for queueing up FP/VEC/VSX unavailable interrupts

This provides functions that can be used for generating interrupts indicating that a given functional unit (floating point, vector, or VSX) is unavailable. These functions will be used in instruction emulation code. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/inclu

[PATCH 0/5] KVM: PPC: Improve MMIO emulation

Guests accessing emulated MMIO can do so using a wide variety of load and store instructions on PPC machines. However, KVM currently only knows about a subset of the load and store instructions available. This patchset expands the set of load and store instructions that KVM can emulate to include

[PATCH] Revert "powerpc/64: Disable use of radix under a hypervisor"

of radix, we clear the MMU_FTR_TYPE_RADIX and then set it again, and print a warning about ignoring the disable_radix command line option, even though the command line does not include "disable_radix". Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- This should go into 4.11.

Re: [PATCH V2 07/11] powerpc/mm: Conditional defines of pte bits are messy

fines was the patch description. For the code change: Reviewed-by: Paul Mackerras <pau...@ozlabs.org>

Re: [PATCH V2 05/11] powerpc/mm: Add translation mode information in /proc/cpuinfo

e: OPAL > MMU : Hash > > Signed-off-by: Aneesh Kumar K.V <aneesh.ku...@linux.vnet.ibm.com> Reviewed-by: Paul Mackerras <pau...@ozlabs.org>

Re: [PATCH V2 09/11] powerpc/mm: Lower the max real address to 51 bits

ng hash linux page table > specific bits to top of RPN field free up the software bits for other purpose. > > Signed-off-by: Aneesh Kumar K.V <aneesh.ku...@linux.vnet.ibm.com> > --- There are a couple of comment typos below, but for the actual code change: Reviewed-by: Paul Mackerras &l

Re: [PATCH V2 03/11] powerpc/mm: Cleanup bits definition between hash and radix.

mar K.V <aneesh.ku...@linux.vnet.ibm.com> Reviewed-by: Paul Mackerras <pau...@ozlabs.org>

Re: [PATCH V2 10/11] powerpc/mm/radix: Make max pfn bits a variable

On Thu, Mar 16, 2017 at 04:02:08PM +0530, Aneesh Kumar K.V wrote: > This makes max pysical address bits a variable so that hash and radix > translation mode can choose what value to use. In this patch we also switch > the > radix translation mode to use 57 bits. This make it resilient to future

Re: [PATCH V2 02/11] powerpc/mm/slice: when computing slice mask limit lowe slice max addr correctly

ode and why your fix is the correct one. > > Signed-off-by: Aneesh Kumar K.V <aneesh.ku...@linux.vnet.ibm.com> For the code change: Reviewed-by: Paul Mackerras <pau...@ozlabs.org>

Re: [PATCH V2 06/11] powerpc/mm/hugetlb: Filter out hugepage size not supported by page table layout

On Thu, Mar 16, 2017 at 04:02:04PM +0530, Aneesh Kumar K.V wrote: > Without this if firmware reports 1MB page size support we will crash > trying to use 1MB as hugetlb page size. > > echo 300 > /sys/kernel/mm/hugepages/hugepages-1024kB/nr_hugepages > > kernel BUG at

Re: [PATCH V2 04/11] powerpc/mm/radix: rename _PAGE_LARGE to R_PAGE_LARGE

> > Signed-off-by: Aneesh Kumar K.V <aneesh.ku...@linux.vnet.ibm.com> Reviewed-by: Paul Mackerras <pau...@ozlabs.org>

Re: [PATCH V2 08/11] powerpc/mm: Express everything based on Radix page table defines

" or something like that? "Everything" is a bit too broad. For the code change: Reviewed-by: Paul Mackerras <pau...@ozlabs.org>

Re: [PATCH V2 11/11] powerpc/mm: Move hash specific pte bits to be top bits of RPN

On Thu, Mar 16, 2017 at 04:02:09PM +0530, Aneesh Kumar K.V wrote: > We don't support the full 57 bits of physical address and hence can overload > the top bits of RPN as hash specific pte bits. > > Signed-off-by: Aneesh Kumar K.V > --- >

Re: [PATCH V2 01/11] powerpc/mm/nohash: MM_SLICE is only used by book3s 64

MM_SLICE. > But that is good, because we reduce one extra variant which probably is not > getting tested much. > > Signed-off-by: Aneesh Kumar K.V <aneesh.ku...@linux.vnet.ibm.com> Reviewed-by: Paul Mackerras <pau...@ozlabs.org>

Re: [PATCH] powerpc/64: Fix checksum folding in csum_add

On Sat, Feb 04, 2017 at 05:03:40PM +0800, Shile Zhang wrote: > fix the missed point in Paul's patch: > "powerpc/64: Fix checksum folding in csum_tcpudp_nofold and > ip_fast_csum_nofold" > > Signed-off-by: Shile Zhang <shile.zh...@nokia.com> Acked-by: Paul Mackerras <pau...@ozlabs.org>

Re: [PATCH V3 2/2] powerpc: Update to new option-vector-5 format for CAS

ecture change request "CAS option vector additions for P9". Apart from that, Acked-by: Paul Mackerras <pau...@ozlabs.org>

Re: [PATCH] KVM: Prevent double-free on HPT resize commit path

On Tue, Feb 28, 2017 at 11:56:55AM +1100, David Gibson wrote: > On Wed, Feb 15, 2017 at 02:40:04PM +1100, David Gibson wrote: > > resize_hpt_release(), called once the HPT resize of a KVM guest is > > completed (successfully or unsuccessfully) free()s the state structure for > > the resize. It is

[PATCH] KVM: PPC: Book3S HV: Fix software walk of guest process page tables

HV: Add basic infrastructure for radix guests") Fixes: e99833448c5f ("powerpc/mm/radix: Add partition table format & callback") Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/book3s/64/mmu.h | 3 ++- arch/powerpc/kvm/book3s_64_mmu_radix.

[PATCH] powerpc/64: Invalidate process table caching after setting process table

entry) instruction with parameters to invalidate caching of the process table after the new process table is installed. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/mm/pgtable-radix.c | 4 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/mm/pgtable-rad

Re: [RFC NO-MERGE 1/2] arch/powerpc/prom_init: Parse the command line before calling CAS

alling > CAS so we can correctly represent which mmu we would like to use. > > Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> Reviewed-by: Paul Mackerras <pau...@ozlabs.org>

Re: [RFC NO-MERGE 2/2] arch/powerpc/CAS: Update to new option-vector-5 format for CAS

On Tue, Feb 21, 2017 at 05:06:11PM +1100, Suraj Jitindar Singh wrote: > The CAS process has been updated to change how the host to guest Once again, explain CAS; perhaps "The ibm,client-architecture-support (CAS) negotiation process has been updated for POWER9 to ..." > negotiation is done for

[PATCH] powerpc/64: Call H_REGISTER_PROC_TBL when running as a HPT guest on POWER9

R_PROC_TBL in this case, before we attempt to create any HPT entries using H_ENTER. Fixes: cc3d2940133d ("powerpc/64: Enable use of radix MMU under hypervisor on POWER9") Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- This needs to go in after the topic/ppc-kvm branch. arch/

[PATCH] powerpc/64: Disable use of radix under a hypervisor

Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/mm/init_64.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c index 93abf8a..8e15880 100644 --- a/arch/powerpc/mm/init_64.c +++ b/arch/powerpc/mm/ini

Re: [PATCH -next] KVM: PPC: Fix error return code in kvm_vm_ioctl_create_spapr_tce()

On Tue, Feb 07, 2017 at 03:34:07PM +, Wei Yongjun wrote: > From: Wei Yongjun > > Fix to return error code -ENOMEM from the memory alloc error handling > case instead of 0, as done elsewhere in this function. > > Signed-off-by: Wei Yongjun >

[PATCH v2] powerpc/powernv: Remove separate entry for OPAL real mode calls

From: Benjamin Herrenschmidt <b...@kernel.crashing.org> All entry points already read the MSR so they can easily do the right thing. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- This version is rebased

Re: [PATCHv2 00/11] KVM implementation of PAPR HPT resizing extension

On Wed, Feb 01, 2017 at 03:56:36PM +1100, David Gibson wrote: > On Wed, Feb 01, 2017 at 09:18:13AM +1100, Paul Mackerras wrote: > > On Tue, Dec 20, 2016 at 04:48:56PM +1100, David Gibson wrote: > > > Here is the KVM implementation for the proposed PAPR extension which > &

Re: [PATCHv2 00/11] KVM implementation of PAPR HPT resizing extension

On Tue, Dec 20, 2016 at 04:48:56PM +1100, David Gibson wrote: > Here is the KVM implementation for the proposed PAPR extension which > allows the runtime resizing of a PAPR guest's Hashed Page Table (HPT). > > Using this requires a guest kernel with support for the extension. > Patches for guest

Re: [PATCH 3/3] KVM: PPC: Book3S: 64-bit CONFIG_RELOCATABLE support for interrupts

On Thu, Dec 22, 2016 at 04:29:27AM +1000, Nicholas Piggin wrote: > 64-bit Book3S exception handlers must find the dynamic kernel base > to add to the target address when branching beyond __end_interrupts, > in order to support kernel running at non-0 physical address. > > Support this in KVM by

Re: [PATCH v2 13/20] KVM: PPC: Book3S HV: Page table construction and page faults for radix guests

On Tue, Jan 31, 2017 at 07:58:57AM +1100, Michael Ellerman wrote: > Paul Mackerras <pau...@ozlabs.org> writes: > > > This adds the code to construct the second-level ("partition-scoped" in > > architecturese) page tables for guests using the radix MMU. A

[PATCH v2 20/20] KVM: PPC: Book3S HV: Enable radix guest support

support radix guests if the host is running in radix mode, and only support HPT guests if the host is running in HPT mode. Thus a guest cannot switch from one mode to the other, which enables some simplifications. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/inclu

[PATCH v2 19/20] KVM: PPC: Book3S HV: Invalidate ERAT on guest entry/exit for POWER9 DD1

On POWER9 DD1, we need to invalidate the ERAT (effective to real address translation cache) when changing the PIDR register, which we do as part of guest entry and exit. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 6 ++ 1 file chan

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