Hi Ben,
> Well... the above is a HW limitation :-) IE. I was suggesting you fix
> the HW, but in the case where you already did and the current MAL in
> your SoC can indeed mask the interrupt per-channel, then that's great
> and we should definitely look into having the driver go back to a more
>
Hi Ben,
>
> BTW. If you guys are ever going to do another change to MAL, please
> please plase, add the -one- major missing feature that's causing all the
> pain and complication in the current design: Add a per-channel interrupt
> masking option.
>
> The lack of ability to mask the interrupt per
Hi Ben,
Thanks again for your comments.
> Same goes with the SDR register definitions. Prefix them with the SOC
> name but don't make them conditionally compiled.
I will add the base address in the Device tree, and make all register
definitions based on offset from the base in the next version of
Hi Ben,
Thanks for your comments.
> What happens if we build a kernel that is supposed to boot with two
> different variants of 405 or 440 ?
We cannot build a kernel with H/W Interrupt coalescing other than in
405EX/460EX/GT.
This is controlled via KConfig (config IBM_NEW_EMAC_INTR_COALESCE
depe
Support for Hardware Interrupt coalescing in MAL.
Coalescing is supported on the newer revs of 460EX/GT and 405EX.
The MAL driver falls back to EOB IRQ if coalescing not supported
Signed-off-by: Prodyut Hazarika
Acked-by: Victor Gallardo
Acked-by: Feng Kan
---
drivers/net/ibm_newemac/Kconfig
Support for MAL interrupt coalescing in Canyonlands, Kilauea & Glacier
dts.
MAL driver falls back to EOB IRQ if Coalescing IRQ mapping missing in dts
Signed-off-by: Prodyut Hazarika
Acked-by: Victor Gallardo
Acked-by: Feng Kan
---
arch/powerpc/boot/dts/canyonlands.dts |6 +-
Datacasting Corporation
>>
>> Mikhail Zolotaryov wrote:
>>> Hi,
>>>
>>> Why manage cache lines manually, if appropriate code is a part of
>>> __dma_sync / dma_sync_single_for_device of DMA API ? (implies
>>> CONFIG_NOT_COHERENT_CACHE enabled, as defaul
izes and reserve a TLB
> in memory as cache inhibited (using the 'I' bit). Will update if this
> works as well. Thanks for your help in this.
Aren't you using dma_alloc_coherent to get buffers that are shared
between CPU and external devices?
Thanks
Prodyut
On Tue, 2009-09-08 a
ou will need to invalidate and flush the lines appropriately,
since in 440 cores,
L1Cache coherency is managed entirely by software.
Please look at drivers/net/ibm_newemac/mal.c and core.c for example on
how to do it.
Thanks
Prodyut
On Thu, 2009-09-03 at 13:27 -0700, Prodyut Hazarika wrote:
> Hi Ada
Hi Adam,
> Are you sure there is L2 cache on the 440?
It depends on the SoC you are using. SoC like 460EX (Canyonlands board)
have L2Cache.
It seems you are using a Sequoia board, which has a 440EPx SoC. 440EPx
has a 440 cpu core, but no L2Cache.
Could you please tell me which SoC you are using?
On Sun, Jan 11, 2009 at 10:42 AM, Yuri Tikhonov wrote:
>
> This patch adds support for 256KB pages on ppc44x-based boards.
>
Hi Yuri,
Do you still need the mm/shmem.c patch to avoid division by zero? I
looked at the mm/shmem.c latest git code, and I see that it doesn't
have the needed patch for 2
> It helps if you CC the person you're writing too :).
Thanks Josh for pointing this out :-) I will be careful in future.
> Anyway, I looked over it briefly and agree it looks pretty good. A bit
> late for 2.6.28, but I'll do a more thorough review and get it in for
> 2.6.29.
>
Great. Look forwar
On Wed, Oct 15, 2008 at 7:22 PM, Ilya Yanok <[EMAIL PROTECTED]> wrote:
> This patch adds support for page sizes bigger than 4K (16K/64K) on
> PPC 44x.
>
This patch looks good to me. Seems that all the review comments have
been incorporated.
Josh, it would be great if this patch is pulled into the
> On Thu, Sep 11, 2008 at 01:53:07AM +0400, Ilya Yanok wrote:
>> ENTRIES_PER_PAGEPAGE define in mm/shmem.c becomes zero if page size is
>> 256KB. This patch fixes this.
>
> This looks.. dubious. You're making a change to generic code for a
> powerpc feature. Plus it's not entirely clear that simp
>/*
> * Create WS1. This is the faulting address (EPN),
> * page size, and valid flag.
> */
> - li r11,PPC44x_TLB_VALID | PPC44x_TLB_4K
> + li r11,PPC44x_TLB_VALID | PPC44x_TLBE_SIZE
>rlwimi r10,r11,0,20,31 /* Insert val
fter I am done with it.
Also, it would be great if you could point me what changes are
necessary to recompile the binutils.
I would like to test the 256KB changes on my Canyonlands board. I have
got 16KB/64KB working.
Regards,
Prodyut Hazarika
___
Lin
>
> I think you missed first '-' on the first line.
>
I was not too careful :-)
>> I think these 44x specific defines should go to asm/mmu-44x.h since I
>>
>
> Agreed.
>
It would be great to have user-friendly names.
Also moving to the mmu-4xx specific header files hides the changes to 4xx files.
I was planning to post a similar patch. Good that you already posted
it :-) I will try to finish off similar patch for 40x processors.
>
> +choice
> + prompt "Page size"
> + depends on 44x && PPC32
> + default PPC32_4K_PAGES
> + help
> + The PAGE_SIZE definition. In
n the Denx kernel. I was in the impression that they
were in the mainline Linux tree too. I will try to get those drivers submitted
to the main Linux tree.
Thanks for your clarifications.
Regards,
Prodyut Hazarika
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Linux
drivers/dma/ppc440spe-adma.c
The usb driver for 4xx used to be under: drivers/usb/gadget/dwc_otg/*
The whole dwc_otg directory got removed.
Do you know the reason why these drivers were removed? Also, are there plans to
get these drivers back?
Please let me kno
d I base my patch from your master branch or your 'next' branch?
Regards,
Prodyut Hazarika
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se my patch from your git tree or Linus's git tree? Please advice
how to proceed since I want your efforts in merging as painless as possible.
Regards,
Prodyut Hazarika
===
Staff S/w Engineer
AMCC
===
___
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le range? The user can mmap a region of memory as
non-cacheable, but then call memcpy with that address.
The optimized version must quickly determine that dcbt/dcbz must not
be used in this case.
I don't know what would be a good way to ach
jump in memxxx function after
using dcbt/dcbz.
Thanks,
Prodyut Hazarika
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; boards, but I don't have them all so any testing you can do would be
> awesome.
I tried pulling up the latest code from your git tree. Seems it is not
yet put in there.
Do I have to manually apply all the patches to my git tree. I was
planning to test the changes on Canyonlands, glacier
Hi all,
I am trying to optimize the __copy_tofrom_user function for PPC4xx,
and I would want to know why the exception handling code has been made
so complicated. All the fixup code should do is to store the number of
bytes that failed in copy in r3 and return back.
The current code tries to copy
Hi all,
I am trying to optimize the __copy_tofrom_user function for PPC4xx,
and I would want to know why the exception handling code has been made
so complicated. All the fixup code should do is to store the number of
bytes that failed in copy in r3 and return back.
The current code tries to copy
TED]> wrote:
> On Thu, 3 Jul 2008 11:54:33 -0700
> "prodyut hazarika" <[EMAIL PROTECTED]> wrote:
>
> > Hi all,
> > I would like to know whether Linux on PowerPC puts the processor on
> > low power mode during idle state. Most PowerPC processors support a
> &
Hi all,
I would like to know whether Linux on PowerPC puts the processor on
low power mode during idle state. Most PowerPC processors support a
low power mode. I am looking to add support for low-power mode in
Linux for AMCC 4xx processors.
My questions are the following:
1) Is tickless kernel int
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