On Fri, 2015-07-31 at 05:59 -0500, Hou Zhiqiang-B48286 wrote:
Hi Dongsheng and Scott,
Do you have any comment?
-Original Message-
From: Zhiqiang Hou [mailto:b48...@freescale.com]
Sent: 2015年7月21日 18:10
To: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org
Cc: Hu
On Fri, 2015-07-31 at 20:53 +0800, Chenhui Zhao wrote:
diff --git a/arch/powerpc/kernel/fsl_booke_entry_mapping.S
b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
index f22e7e4..32ec426f 100644
--- a/arch/powerpc/kernel/fsl_booke_entry_mapping.S
+++
On Fri, 2015-07-24 at 20:46 +0800, Chenhui Zhao wrote:
+static void mpc85xx_pmc_set_wake(struct device *dev, void *enable)
{
int ret;
+ u32 value[2];
+
+ if (!device_may_wakeup(dev))
+ return;
+
+ if (!pmc_regs) {
+ dev_err(dev, %s: PMC is
[Added KVM lists and a couple relevant people]
On Fri, 2015-07-31 at 14:25 +0530, Hemant Kumar wrote:
On 07/30/2015 03:52 AM, Scott Wood wrote:
On Wed, 2015-07-29 at 16:07 +0530, Hemant Kumar wrote:
Hi Scott,
On 07/17/2015 01:40 AM, Scott Wood wrote:
On Thu, 2015-07-16 at 21:18
On Thu, 2015-07-30 at 07:47 +0300, Igal.Liberman wrote:
From: Igal Liberman igal.liber...@freescale.com
Describe the PHY topology for all configurations supported by each board
Based on prior work by Andy Fleming aflem...@freescale.com
Signed-off-by: Igal Liberman
On Thu, 2015-07-30 at 07:32 +0300, Igal.Liberman wrote:
+fman0: fman@40{
+ #address-cells = 1;
+ #size-cells = 1;
+ cell-index = 0;
+ compatible = fsl,fman;
+ ranges = 0 0x40 0x10;
+ reg = 0x40 0x10;
+ interrupts = 96 2 0 0, 16 2 1 1;
+
On Thu, 2015-07-30 at 07:33 +0300, Igal.Liberman wrote:
@@ -307,4 +307,117 @@
reg = 0xe 0x1000;
fsl,has-rstcr;
};
+
+ fman@10{
+ #address-cells = 1;
+ #size-cells = 1;
+ cell-index = 0;
+
on a fragment-generated config).
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/configs/corenet32_smp_defconfig | 97
arch/powerpc/configs/corenet64_smp_defconfig | 97 +---
arch/powerpc/configs/mpc85xx_defconfig | 40
These patches sit on top of the following patches:
http://patchwork.ozlabs.org/patch/499211/
http://patchwork.ozlabs.org/patch/499200/
http://patchwork.ozlabs.org/patch/468592/
Scott Wood (2):
powerpc/85xx: Make defconfigs consistent
powerpc/85xx: Use kconfig fragments
arch/powerpc/Makefile
previously selected. No attempt was made in this (or
the previous) patch to edit out questionable options, but this patch
will make it easier to do so in future patches.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/Makefile| 20 ++
arch/powerpc/configs
On Wed, 2015-07-29 at 20:27 -0500, Zhao Qiang-B45475 wrote:
On Thu, 2015-07-30 at 5:21, Scott Wood wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, July 30, 2015 12:19 AM
To: Zhao Qiang-B45475
Cc: lau...@codeaurora.org; linux-ker...@vger.kernel.org; linuxppc
On Wed, 2015-07-29 at 10:02 +0200, Arnd Bergmann wrote:
On Wednesday 29 July 2015 00:24:37 Scott Wood wrote:
+#ifdef CONFIG_PM
static void lock_tx_qs(struct gfar_private *priv)
{
int i;
@@ -580,6 +581,7 @@ static void unlock_tx_qs(struct gfar_private *priv)
for (i = 0; i
On Tue, 2015-07-28 at 00:32 -0500, Zhao Qiang-B45475 wrote:
On Tue, 2015-07-28 at 5:21, Scott Wood wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, July 28, 2015 5:21 AM
To: Zhao Qiang-B45475
Cc: lau...@codeaurora.org; linux-ker...@vger.kernel.org; linuxppc-
d
On Wed, 2015-07-29 at 16:07 +0530, Hemant Kumar wrote:
Hi Scott,
On 07/17/2015 01:40 AM, Scott Wood wrote:
On Thu, 2015-07-16 at 21:18 +0530, Hemant Kumar wrote:
To analyze the exit events with perf, we need kvm_perf.h to be added in
the arch/powerpc directory, where the kvm
On Wed, 2015-07-29 at 04:07 -0500, Jain Priyanka-B32167 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Friday, July 24, 2015 8:58 PM
To: Jain Priyanka-B32167
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH][v2] powerpc/fsl-booke: Add T1040D4RDB/T1042D4RDB
On Tue, 2015-07-28 at 21:34 -0500, Hou Zhiqiang-B48286 wrote:
Hi Scott and all,
Please ignore this patch!
Did you figure out what was actually causing you to see CPU stalls?
-Scott
___
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, but the rfbptr code has deeper
issues. It uses the virtual address as the DMA address, which again,
happens to work in the environments where this driver is currently
used, but is not the right thing to do.
Signed-off-by: Scott Wood scottw...@freescale.com
---
Alternatively, if there's a desire to not mess
On Fri, 2015-07-24 at 10:45 -0500, Bucur Madalin-Cristian-B32716 wrote:
-Original Message-
From: Joe Perches [mailto:j...@perches.com]
On Wed, 2015-07-22 at 19:16 +0300, Madalin Bucur wrote:
+static int __init dpa_load(void)
+{
[]
+ err =
On Mon, 2015-07-27 at 09:58 +0200, Ulf Hansson wrote:
On 25 July 2015 at 04:27, Scott Wood scottw...@freescale.com wrote:
On Tue, 2015-07-21 at 15:02 +0200, Ulf Hansson wrote:
On 21 July 2015 at 11:45, Yangbo Lu yangbo...@freescale.com wrote:
For T4240-R1.0-R2.0, the HOSTVER register has
On Mon, 2015-07-27 at 17:57 +0800, Zhao Qiang wrote:
diff --git a/lib/genalloc.c b/lib/genalloc.c
index d214866..e6608cd 100644
--- a/lib/genalloc.c
+++ b/lib/genalloc.c
@@ -509,6 +509,31 @@ unsigned long gen_pool_first_fit(unsigned long *map,
unsigned long size,
On Mon, 2015-07-27 at 14:26 +0800, liulijun wrote:
I've been struggling with a kernel panic during enumeration of a Rapid IO
system.
I am using the AM4140 with Freescale P4080 processor. The Linux
kernel'version is 2.6.34.6.
That is a very old kernel. If you're using that old kernel
On Mon, 2015-07-20 at 01:43 -0500, Lu Yangbo-B47093 wrote:
OK, thanks. Assuming no similar issues when testing, I'll apply this
patch the next time I do a batch of patch application.
Any thoughts regarding better error handling?
-Scott
Do you mean SD test?
I just mean that I
On Mon, 2015-07-20 at 15:32 +0800, Zhao Qiang wrote:
From: Zhao Qiang b45...@freescale.com
p1010rdb-pb use the irq[4:5] for inta and intb to pcie,
it is active-high, so set it.
What about revisions of p1010rdb other than pb?
Signed-off-by: Zhao Qiang b45...@freescale.com
Change-Id:
On Wed, 2015-07-22 at 05:49 -0500, Jain Priyanka-B32167 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Friday, July 17, 2015 10:37 PM
To: Jain Priyanka-B32167
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH][v2] powerpc/fsl-booke: Add T1040D4RDB/T1042D4RDB
On Mon, 2015-07-20 at 01:33 -0500, Lu Yangbo-B47093 wrote:
On Wed, 2015-07-15 at 21:37 -0500, Lu Yangbo-B47093 wrote:
Any comments?
Thanks.
Sorry, I must have missed this on my last time through the patch queue.
I see you've decimalized the fiper and max-adj properties, which is
On Wed, 2015-07-22 at 18:08 +0800, Zhiqiang Hou wrote:
From: Hou Zhiqiang b48...@freescale.com
You CCed this to
b21...@freescale.com. Who is that? It would be nice to use friendly
e-mail addresses, but at least include the name along with the e-mail address.
I suggest CCing the people who
On Tue, 2015-07-21 at 15:02 +0200, Ulf Hansson wrote:
On 21 July 2015 at 11:45, Yangbo Lu yangbo...@freescale.com wrote:
For T4240-R1.0-R2.0, the HOSTVER register has incorrcet vender
version value and sdhc spec version value. This will break down
the ADMA data transfer. So add workaround
On Tue, 2015-07-21 at 17:45 +0800, Yangbo Lu wrote:
Add 'cpu-rev' property for cpus node to support getting cpu revision
from dts, since it's not good to get cpu revision using powerpc specific
function(like SVR_REV()) in common drivers.
No. Don't modify the device tree within Linux without a
the fact that the hard reset is done on 32-bit
kexec, and I especially don't like the timebase sync being triggered
only on the presence of CONFIG_KEXEC rather than actually booting in
that environment, but that's beyond the scope of this patch...
Signed-off-by: Scott Wood scottw...@freescale.com
From: Tiejun Chen tiejun.c...@windriver.com
Rename 'interrupt_end_book3e' to '__end_interrupts' so that the symbol
can be used by both book3s and book3e.
Signed-off-by: Tiejun Chen tiejun.c...@windriver.com
[scottwood: edit changelog]
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch
with
the kernel at zero and thus skip copy_to_flush -- but it will be
needed for kexec support.
Signed-off-by: Tiejun Chen tiejun.c...@windriver.com
[scottwood: split patch and rewrote changelog]
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/kernel/head_64.S | 11 +++
1 file
book3e_secondary_core_init will only create a TLB entry if r4 = 0,
so do so.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/kernel/misc_64.S | 4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index c5915f0
From: Tiejun Chen tiejun.c...@windriver.com
Allow KEXEC for book3e, and bypass or convert non-book3e stuff
in kexec code.
Signed-off-by: Tiejun Chen tiejun.c...@windriver.com
[scottw...@freescale.com: move code to minimize diff, and cleanup]
Signed-off-by: Scott Wood scottw...@freescale.com
long arguments to be passed as int.
Signed-off-by: Scott Wood scottw...@freescale.com
---
kexec/arch/ppc64/crashdump-ppc64.c | 3 ++-
kexec/arch/ppc64/kexec-elf-ppc64.c | 9 +
2 files changed, 3 insertions(+), 9 deletions(-)
diff --git a/kexec/arch/ppc64/crashdump-ppc64.c
b/kexec/arch
-July/014048.html (ppc64:
Add a flag to tell the kernel it's booting from kexec).
Scott Wood (11):
powerpc/85xx: Load all early TLB entries at once
powerpc/85xx: Don't use generic timebase sync on 64-bit
crypto: caam: Blacklist CAAM when kexec is enabled
powerpc/fsl-corenet: Disable coreint
-off-by: Scott Wood scottw...@freescale.com
---
Supposedly there are similar problems with certain low power states --
the SDK disables coreint when CPU hotplug is enabled -- so disabling it
for kexec as well doesn't seem like a big deal.
---
arch/powerpc/platforms/85xx/corenet_generic.c | 4
This driver hangs the kernel on boot when loaded via kexec.
To make this driver kexec-safe, add a suspend or freeze hook, and when
probing, don't make any assumptions about the existing hardware state
(e.g. don't request_irq before quiescing the device).
Signed-off-by: Scott Wood scottw
The new kernel will be expecting secondary threads to be disabled,
not spinning.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/kernel/head_64.S | 16 +
arch/powerpc/platforms/85xx/smp.c | 48 +++
2 files changed, 64
From: Tiejun Chen tiejun.c...@windriver.com
Unlike 32-bit 85xx kexec, we don't do a core reset.
Signed-off-by: Tiejun Chen tiejun.c...@windriver.com
[scottwood: edit changelog, and cleanup]
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/platforms/85xx/smp.c | 11
This limit only makes sense on book3s, and on book3e it can cause
problems with kdump if we don't have any memory under 256 MiB.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/kernel/paca.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc
communication between the kernel and kexec to set that up.
Since there's already a similar flag being set (for kdump only), this
seemed like a reasonable approach.
Signed-off-by: Scott Wood scottw...@freescale.com
---
kexec/arch/ppc64/kexec-elf-ppc64.c | 11 ++-
kexec/arch/ppc64/kexec-ppc64.h
want another thread to be running when we
create a temporary trampoline TLB1 entry.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/kernel/setup_64.c | 8 +
arch/powerpc/mm/fsl_booke_mmu.c | 15 --
arch/powerpc/mm/mmu_decl.h | 1 +
arch/powerpc/mm
that does. Thus, more TLB entries are needed than
would normally be used, as the total memory to be mapped might not be a
power of two.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/mm/fsl_booke_mmu.c | 22 +++---
arch/powerpc/mm/mmu_decl.h | 3 ++-
arch
kernel, we should reset ipvr properly again
after .relocate.
Signed-off-by: Tiejun Chen tiejun.c...@windriver.com
[scottwood: cleanup and ifdef removal]
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/include/asm/exception-64e.h | 4 ++--
arch/powerpc/kernel/exceptions-64e.S
While book3e doesn't have real mode, we still want to wait for
all the non-crash cpus to complete their shutdown.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/kernel/crash.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel
/patch/257657/
(book3e/kexec/kdump: introduce a kexec kernel flag), this flag is at
a fixed address for ABI stability, and actually gets set properly in
the kdump case (i.e. on the crash kernel, not on the crashing kernel).
Signed-off-by: Scott Wood scottw...@freescale.com
---
This depends
From: Tiejun Chen tiejun.c...@windriver.com
book3e has no real MMU mode so we have to create an identity TLB
mapping to make sure we can access the real physical address.
Signed-off-by: Tiejun Chen tiejun.c...@windriver.com
[scottwood: cleanup, and split off some changes]
Signed-off-by: Scott
booke-32 will use VIRT_PHYS_OFFSET, so given the
issues with its calculation, restrict its definition to booke-32.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/include/asm/page.h | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm
to real address table)
which allows KVM guests to control the WIMGE bits. This means that
KVM cannot force the M bit on the way it usually does, so the guest had
better set it itself.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/include/asm/pte-common.h | 3 ++-
arch
map_kernel() doesn't catch all places that create kernel PTEs. In
particular, vmalloc() calls set_pte_at() directly. This causes a
crash when booting a non-SMP kernel on e6500.
Move the sync to __set_pte(), to be executed only for kernel addresses.
Signed-off-by: Scott Wood scottw
On Fri, 2015-07-17 at 01:17 -0500, Jain Priyanka-B32167 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Friday, July 17, 2015 1:06 AM
To: Jain Priyanka-B32167
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH][v2] powerpc/fsl-booke: Add T1040D4RDB/T1042D4RDB
On Wed, 2015-07-15 at 21:37 -0500, Lu Yangbo-B47093 wrote:
Any comments?
Thanks.
Sorry, I must have missed this on my last time through the patch queue. I
see you've decimalized the fiper and max-adj properties, which is good... but
does it really make sense for tmr-add? I'm not familiar
OK, thanks. Assuming no similar issues when testing, I'll apply this patch
the next time I do a batch of patch application.
Any thoughts regarding better error handling?
-Scott
On Wed, 2015-07-15 at 21:37 -0500, Lu Yangbo-B47093 wrote:
Hi Scott,
Now the patch below has been merged on
On Thu, 2015-07-16 at 21:18 +0530, Hemant Kumar wrote:
To analyze the exit events with perf, we need kvm_perf.h to be added in
the arch/powerpc directory, where the kvm tracepoints needed to trace
the KVM exit events are defined.
This patch adds kvm_perf_book3s.h to indicate that the
On Thu, 2015-07-16 at 04:34 -0500, Jain Priyanka-B32167 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, July 15, 2015 11:17 PM
To: Jain Priyanka-B32167
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH][v2] powerpc/fsl-booke: Add T1040D4RDB/T1042D4RDB board
it anyway (which is not something you want to
only find out once the main kernel has crashed in the field, especially
if whether it works or not depends on which cpu crashed).
Signed-off-by: Scott Wood scottw...@freescale.com
Cc: Tang Yuantian yuantian.t...@freescale.com
---
I'm sending this before
On Wed, 2015-07-15 at 15:00 +0530, Priyanka Jain wrote:
T1040D4RDB/T1042D4RDB are Freescale Reference Design Board
which can support T1040/T1042 QorIQ Power
Architecture™ processor respectively
T1040D4RDB/T1042D4RDB board Overview
-
- SERDES Connections,
On Sun, 2015-07-12 at 00:47 -0500, Priyanka Jain wrote:
+/ {
+ model = fsl,T1040D4RDB;
+ compatible = fsl,T1040D4RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ ifc: localbus@ffe124000{
+ cpld@3,0 {
+
On Fri, 2015-07-10 at 13:36 +0200, Paul Bolle wrote:
On do, 2015-07-09 at 16:21 -0400, Roy Pledge wrote:
+#ifdef CONFIG_FSL_DPA_CHECKING
+#define DPA_ASSERT(x) \
+ do { \
+ if (!(x)) { \
+ pr_crit(ASSERT: (%s:%d) %s\n, __FILE__, __LINE__, \
+
On Fri, 2015-07-10 at 13:29 -0500, Pledge Roy-R01356 wrote:
return in_be32((void *)bm + offset);
^
[...]/drivers/soc/fsl/qbman/bman.c: In function ‘__bm_out’:
[...]/drivers/soc/fsl/qbman/bman.c:172:2: error: implicit declaration
of function ‘out_be32’
On Fri, 2015-07-10 at 10:38 +0200, Paul Bolle wrote:
On do, 2015-07-09 at 16:21 -0400, Roy Pledge wrote:
--- /dev/null
+++ b/drivers/soc/fsl/qbman/Kconfig
@@ -0,0 +1,33 @@
+menuconfig FSL_DPA
+ bool Freescale DPAA support
+ depends on FSL_SOC || COMPILE_TEST
Are you sure about
On Fri, 2015-07-10 at 15:57 -0500, Pledge Roy-R01356 wrote:
On Fri, 2015-07-10 at 13:36 +0200, Paul Bolle wrote:
On do, 2015-07-09 at 16:21 -0400, Roy Pledge wrote:
+#ifdef CONFIG_FSL_DPA_CHECKING
+#define DPA_ASSERT(x) \
+ do { \
+ if (!(x)) { \
+
On Thu, 2015-07-09 at 01:05 -0500, Zhao Qiang-B45475 wrote:
On Wed, 2015-07-09 at 11:51 -0500, Wood Scott wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, July 09, 2015 11:51 AM
To: Zhao Qiang-B45475
Cc: linuxppc-dev@lists.ozlabs.org; Xie Xiaobo-R63061
On Thu, 2015-07-09 at 01:14 -0500, Zhao Qiang-B45475 wrote:
On Wed, 2015-07-09 at 02:09PM -0500, Wood Scott wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, July 09, 2015 2:09 PM
To: Zhao Qiang-B45475
Cc: linuxppc-dev@lists.ozlabs.org; Xie Xiaobo-R63061
On Thu, 2015-07-09 at 10:42 -0500, Segher Boessenkool wrote:
On Tue, Jul 07, 2015 at 11:22:08PM -0500, Scott Wood wrote:
I agree about using labels, but bcl 20,31,foo is not the same thing
as bl foo. The former is a form of bl that doesn't perturb the link
stack and is therefore better
to manage muram.
Now it support both arm(ls1021,ls1043,ls2085 and such on) and powerpc,
the code need to move from arch/powerpc to public direcory,
Scott wood hopes to use genalloc to manage the muram, after discussing
with scott, we decide to add gen_pool_alloc_align to meet the requirement
On Thu, 2015-07-09 at 03:00 -0500, Jia Hongtao-B38951 wrote:
Hi Scott,
Patch updated to V3, please help to review.
Thanks.
---
Best Regards,
Hongtao
It looks OK.
-Scott
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On Thu, 2015-07-09 at 15:47 +0800, Zhao Qiang wrote:
@@ -541,13 +562,14 @@ EXPORT_SYMBOL(gen_pool_first_fit_order_align);
* which we can allocate the memory.
*/
unsigned long gen_pool_best_fit(unsigned long *map, unsigned long size,
- unsigned long start, unsigned int nr,
On Wed, 2015-07-08 at 14:37 +1000, Samuel Mendoza-Jonas wrote:
If the target kernel does not inlcude the FIXUP_ENDIAN check, coming
from a different-endian kernel will cause the target kernel to panic.
All ppc64 kernels can handle starting in big-endian mode, so return to
big-endian before
On Wed, 2015-07-08 at 22:18 -0500, Zhao Qiang-B45475 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, July 09, 2015 2:59 AM
To: Zhao Qiang-B45475
Cc: linuxppc-dev@lists.ozlabs.org; Xie Xiaobo-R63061
Subject: Re: [PATCH 2/2] rheap: move rheap.c from
On Wed, 2015-07-08 at 02:25 -0500, Zhao Qiang-B45475 wrote:
So I will add two func for my use, do you think it is ok?
I need to align the address of allocated muram.
And I will set algo = gen_pool_first_fit_align.
+unsigned long gen_pool_alloc_align(struct gen_pool *pool, size_t size,
+
On Tue, 2015-07-07 at 16:05 +0800, wenwei tao wrote:
Hi Scott
I understand what you said.
I will use the function 'is_vm_hugetlb_page()' to hide the bit
combinations according to your comments in the next version of patch
set.
But for the situation like below, there isn't an obvious
On Tue, 2015-07-07 at 15:51 +0800, Dongsheng Wang wrote:
From: Wang Dongsheng dongsheng.w...@freescale.com
Move fsl_diu_init into diu probe function, because it should be
initialized when system get diu device tree node, not always do
initialization.
Signed-off-by: Wang Dongsheng
On Wed, 2015-07-08 at 11:23 +1000, Samuel Mendoza-Jonas wrote:
If the target kernel does not inlcude the FIXUP_ENDIAN check, coming
from a different-endian kernel will cause the target kernel to panic.
All ppc64 kernels can handle starting in big-endian mode, so return to
big-endian before
On Tue, 2015-07-07 at 21:46 -0500, Wang Dongsheng-B40534 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, July 08, 2015 10:41 AM
To: Wang Dongsheng-B40534
Cc: Sun York-R58495; linuxppc-dev@lists.ozlabs.org; Jin Zhengxiong-R64188
Subject: Re: [RESEND]
On Tue, 2015-07-07 at 21:30 -0500, Wang Dongsheng-B40534 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, July 08, 2015 5:51 AM
To: Wang Dongsheng-B40534
Cc: Sun York-R58495; linuxppc-dev@lists.ozlabs.org; Jin Zhengxiong-R64188
Subject: Re: [RESEND]
On Tue, 2015-07-07 at 21:54 -0500, Zhao Qiang-B45475 wrote:
I need to ensure one thing,
In your point, you want me to use lib/genalloc.c instead of rheap.c.
Or just think rheap.c is not proper to put into lib?
Best Regards
Zhao Qiang
I want you to use lib/genalloc.c.
-Scott
On Tue, 2015-07-07 at 22:26 -0500, Zhao Qiang-B45475 wrote:
Now the point is, genalloc is not so proper to qe muram while rheap is
written to manage muram,
rheap is not specific to muram.
if use genalloc instead of rheap, there will be amounts of work to do.
Not much. I think I've spent
On Wed, 2015-07-08 at 13:29 +1000, Samuel Mendoza-Jonas wrote:
Older big-endian ppc64 kernels don't include the FIXUP_ENDIAN check,
meaning if we kexec from a little-endian kernel the target kernel will
fail to boot.
Returning to big-endian before we enter the target kernel ensures that
the
On Wed, 2015-07-08 at 14:04 +1000, Paul Mackerras wrote:
On Tue, Jul 07, 2015 at 09:35:38PM -0500, Scott Wood wrote:
Also, it would be better to use label subtraction rather than hardcoding
28, and the bcl instruction would be more readable as bl label.
I agree about using labels
On Fri, 2015-07-03 at 16:47 +0800, wenwei tao wrote:
Hi Scott
Thank you for your comments.
Kernel already has that function: is_vm_hugetlb_page() , but the
original code didn't use it,
in order to keep the coding style of the original code, I didn't use it
either.
For the sentence
On Fri, 2015-07-03 at 17:50 +0800, Shengzhou Liu wrote:
Add support for INA220 current sense.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/t1024rdb.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/boot/dts/t1024rdb.dts
On Thu, 2015-07-02 at 10:32 -0500, Liberman Igal-B31950 wrote:
Hi Scott,
Thank you for your feedback, please take a look at my comments/questions.
Regards,
Igal Liberman.
-Original Message-
From: Wood Scott-B07421
Sent: Friday, June 26, 2015 6:55 AM
To: Liberman Igal-B31950
On Wed, 2015-06-10 at 14:27 +0800, Wenwei Tao wrote:
Hugetlb VMAs are not mergeable, that means a VMA couldn't have VM_HUGETLB
and
VM_MERGEABLE been set in the same time. So we use VM_HUGETLB to indicate new
mergeable VMAs. Because of that a VMA which has VM_HUGETLB been set is a
hugetlb
Why are these two parts being submitted separately? Worse, the CC list seems
to be different for each part as I'm not seeing the DPAA ETH driver.
-Scott
On Sun, 2015-06-28 at 03:06 -0500, Liberman Igal-B31950 wrote:
Hi Paul,
All those exported functions are used by DPAA ETH driver, which was
On Fri, 2015-06-26 at 12:21 +1000, Michael Ellerman wrote:
On Thu, 2015-06-25 at 19:59 -0500, Scott Wood wrote:
On Fri, 2015-06-26 at 01:06 +0200, Paul Bolle wrote:
(Evolution 3.16 is basically unbearable for replying to patches.
Anyone
else running into this?)
If you mean
On Wed, 2015-06-24 at 22:35 +0300, igal.liber...@freescale.com wrote:
From: Igal Liberman igal.liber...@freescale.com
Add Frame Manger Driver support.
This patch adds The FMan configuration, initialization and
runtime control routines.
Signed-off-by: Igal Liberman
On Tue, 2015-06-23 at 16:07 +0800, yuantian.t...@freescale.com wrote:
From: Tang Yuantian yuantian.t...@freescale.com
There is a RCPM (Run Control/Power Management) in Freescale QorIQ
series processors. The device performs tasks associated with device
run control and power management.
The
On Wed, 2015-06-24 at 22:34 +0300, igal.liber...@freescale.com wrote:
From: Igal Liberman igal.liber...@freescale.com
The FMan MAC FLib provides basic API used by the drivers to
configure and control the FMan MAC hardware.
Signed-off-by: Igal Liberman igal.liber...@freescale.com
...
+int
On Fri, 2015-06-26 at 01:06 +0200, Paul Bolle wrote:
(Evolution 3.16 is basically unbearable for replying to patches.
Anyone
else running into this?)
If you mean the crazy lag when selecting moderate-to-large amounts of
text (for snipping), yes.
-Scott
On Wed, 2015-06-24 at 22:33 +0300, igal.liber...@freescale.com wrote:
From: Igal Liberman igal.liber...@freescale.com
The FMan FLib provides the basic API used by the FMan drivers to
configure and control the FMan hardware.
Signed-off-by: Igal Liberman igal.liber...@freescale.com
Again,
On Wed, 2015-06-24 at 22:34 +0300, igal.liber...@freescale.com wrote:
+ struct muram_info *p_muram;
No Hungarian notation.
+void fm_muram_free(struct muram_info *p_muram)
+{
+ /* Destroy pool */
+ gen_pool_destroy(p_muram-pool);
+ /* Unmap memory */
+
On Mon, 2015-06-22 at 19:01 +0200, Christophe Leroy wrote:
The powerpc64 checksum wrapper functions adds the
csum_and_copy_to_user() which
otherwise is implemented in include/net/checksum.h by using
csum_partial() then
copy_to_user()
Those two wrapper fonctions are also applicable to
describing its individual registers.
For more detail, see the commit message of patch 4.
Scott Wood (8):
ARM: dts: ls1021a: Fix clockgen node
cpufreq: qoriq: Don't look at clock implementation details
powerpc/fsl: Move fsl_guts.h out of arch/powerpc
clk: qoriq: Move chip-specific knowledge
to continue working once the clocks
are generated based on the clock driver's knowledge of the chip
rather than a fragile device-tree description of the mux options.
Signed-off-by: Scott Wood scottw...@freescale.com
---
drivers/cpufreq/qoriq-cpufreq.c | 47 -
1 file
the sysclk node.
Signed-off-by: Scott Wood scottw...@freescale.com
Cc: Jingchang Lu b35...@freescale.com
Cc: Shawn Guo shawn@linaro.org
---
arch/arm/boot/dts/ls1021a.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index
will be ignored, but clocks properties pointing at the old nodes will
still work.
This also lets us get rid of most of the legacy code.
Signed-off-by: Scott Wood scottw...@freescale.com
---
drivers/clk/clk-qoriq.c | 348
1 file changed, 54 insertions(+), 294
to work. This patch does not remove
the code for handling the old nodes. A subsequent patch removes that
code, but still binds against those nodes and redirects clock lookups
to the clocks generated by the new code.
Signed-off-by: Scott Wood scottw...@freescale.com
---
.../devicetree/bindings/clock
.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 4 +-
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 8 +--
arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 15 --
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi| 18 ---
arch/powerpc
Freescale's Layerscape ARM chips use the same structure.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 2 +-
arch/powerpc/platforms/85xx/p1022_ds.c
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