Thanks for your review.
-Original Message-
From: Wood Scott-B07421
Sent: 2013年10月29日 星期二 11:26
To: Tang Yuantian-B29983
Cc: Wood Scott-B07421; Mark Rutland; devicet...@vger.kernel.org;
linuxppc-dev@lists.ozlabs.org; Li Yang-Leo-R58472
Subject: Re: [PATCH v5] powerpc/mpc85xx: Update
+1. Clock Block Binding
+
+Required properties:
+- compatible: Should include one or more of the following:
+ - fsl,chip-clockgen: for chip specific clock block
+ - fsl,qoriq-clockgen-[1,2].x: for chassis 1.x and 2.x clock
+- reg: Offset and length of the clock register set
+-
Thanks for your review.
-Original Message-
From: Mark Rutland [mailto:mark.rutl...@arm.com]
Sent: 2013年10月21日 星期一 17:15
To: Tang Yuantian-B29983
Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;
devicet...@vger.kernel.org; Li Yang-Leo-R58472
Subject: Re: [PATCH v5
It's still selecting from multiple PLLs.
I don't know whether divider module exists or not. If it
exists, it should be part of PLL or between PLL and MUX.
wherever it was, the
device tree binding is appropriate.
The device tree binding is
On Wed, 2013-10-16 at 21:08 -0500, Tang Yuantian-B29983 wrote:
That shows the dividers as being somewhere in between the PLL
and the
MUX.
The MUX is where the divider is selected. There's nothing in
the PLL's programming interface that relates to the dividers
That shows the dividers as being somewhere in between the PLL and the
MUX.
The MUX is where the divider is selected. There's nothing in the
PLL's programming interface that relates to the dividers. As such
it's simpler to model it as being part of the MUX.
-Scott
I don't
Thanks for your review.
-Original Message-
From: Wood Scott-B07421
Sent: 2013年10月12日 星期六 3:07
To: Mark Rutland
Cc: Tang Yuantian-B29983; devicet...@vger.kernel.org; linuxppc-
d...@lists.ozlabs.org; Li Yang-Leo-R58472
Subject: Re: [PATCH v5] powerpc/mpc85xx: Update the clock nodes
Thanks for your review.
-Original Message-
From: Wood Scott-B07421
Sent: 2013年10月12日 星期六 3:08
To: Tang Yuantian-B29983
Cc: ga...@kernel.crashing.org; devicet...@vger.kernel.org; linuxppc-
d...@lists.ozlabs.org
Subject: Re: [PATCH v5] powerpc/mpc85xx: Update the clock nodes
Thanks for your review.
+- reg: Offset and length of the clock register set
+- clock-frequency: Indicates input clock frequency of clock block.
+ Will be set by u-boot
Why does the fact this is set by u-boot matter to the binding?
OK, I will remove it.
+
Thanks for your review.
See my reply inline
-Original Message-
From: Mark Rutland [mailto:mark.rutl...@arm.com]
Sent: 2013年10月10日 星期四 18:04
To: Tang Yuantian-B29983
Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;
devicet...@vger.kernel.org; Li Yang-Leo-R58472
Subject
On Wed, 2013-09-11 at 20:31 -0500, Tang Yuantian-B29983 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: 2013年9月12日 星期四 9:10
To: Tang Yuantian-B29983
Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;
devicet...@vger.kernel.org; Li Yang
-Original Message-
From: Wood Scott-B07421
Sent: 2013年9月12日 星期四 22:44
To: Tang Yuantian-B29983
Cc: Wood Scott-B07421; ga...@kernel.crashing.org; linuxppc-
d...@lists.ozlabs.org; devicet...@vger.kernel.org; Li Yang-Leo-R58472
Subject: Re: [PATCH v4] powerpc/mpc85xx: Update the clock
-Original Message-
From: Wood Scott-B07421
Sent: 2013年9月12日 星期四 9:10
To: Tang Yuantian-B29983
Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;
devicet...@vger.kernel.org; Li Yang-Leo-R58472
Subject: Re: [PATCH v4] powerpc/mpc85xx: Update the clock device tree
nodes
OK, will update per your suggestions.
Thanks,
Yuantian
-Original Message-
From: Wood Scott-B07421
Sent: 2013年9月11日 星期三 5:47
To: Tang Yuantian-B29983
Cc: Wood Scott-B07421; ga...@kernel.crashing.org;
devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Mike Turquette
Subject
-Original Message-
From: Wood Scott-B07421
Sent: 2013年9月6日 星期五 2:41
To: Tang Yuantian-B29983
Cc: Yang,Wei; Jia Hongtao-B38951; Wood Scott-B07421; linuxppc-
d...@lists.ozlabs.org
Subject: Re: [PATCH] powerpc: Add I2C bus multiplexer node for B4 and
T4240QDS
On Tue, 2013-09-03
Hi,
These eeproms are never used by kernel. So no need to add them.
Thanks,
Yuantian
-Original Message-
From: Linuxppc-dev [mailto:linuxppc-dev-
bounces+b29983=freescale@lists.ozlabs.org] On Behalf Of Yang,Wei
Sent: 2013年9月4日 星期三 9:27
To: Jia Hongtao-B38951
Cc: Wood
Hi,
I noticed that there are already some nodes in i2c bus.
You should at least move the existing node into PCA9547.
Thanks,
Yuantian
-Original Message-
From: Linuxppc-dev [mailto:linuxppc-dev-
bounces+b29983=freescale@lists.ozlabs.org] On Behalf Of Jia Hongtao-
B38951
Sent:
+ };
+ pll1: pll1@820 {
+ #clock-cells = 1;
+ reg = 0x820;
+ compatible = fsl,core-pll-clock;
+ clocks = clockgen;
+
clockgen: global-utilities@e1000 {
- compatible = fsl,b4420-clockgen, fsl,qoriq-clockgen-2.0;
+ compatible = fsl,b4420-clockgen, fsl,qoriq-clockgen-2.0,
+ fixed-clock;
+ clock-output-names = sysclk;
+
Hi Grant.likely,
I really preciate if you can spend some times to review this patch.
Thanks,
Yuantian
-Original Message-
From: Tang Yuantian-B29983
Sent: 2013年4月10日 11:37
To: grant.lik...@secretlab.ca
Cc: rob.herr...@calxeda.com; devicetree-disc...@lists.ozlabs.org; linux-
ker
Hi Mike,
I really appreciate if you can spend some times to review this patch.
Thanks,
Yuantian
-Original Message-
From: Tang Yuantian-B29983
Sent: 2013年4月9日 16:46
To: mturque...@linaro.org
Cc: linus.wall...@linaro.org; viresh.ku...@linaro.org;
shawn@linaro.org; ulf.hans
OK, thanks.
Thanks,
Yuantian
-Original Message-
From: Mike Turquette [mailto:mturque...@linaro.org]
Sent: 2013年4月17日 6:27
To: Tang Yuantian-B29983; Tang Yuantian-B29983
Cc: linus.wall...@linaro.org; viresh.ku...@linaro.org;
shawn@linaro.org; ulf.hans...@linaro.org; linux-
ker
-Original Message-
From: Timur Tabi [mailto:ti...@tabi.org]
Sent: 2013年4月16日 19:37
To: Tang Yuantian-B29983
Cc: Grant Likely; devicetree-discuss; linuxppc-dev@lists.ozlabs.org; lkml;
Rob Herring
Subject: Re: [PATCH v2] of/base: release the node correctly
-Original Message-
From: Timur Tabi [mailto:ti...@tabi.org]
Sent: 2013年4月17日 11:31
To: Tang Yuantian-B29983
Cc: Grant Likely; devicetree-discuss; linuxppc-dev@lists.ozlabs.org; lkml;
Rob Herring
Subject: Re: [PATCH v2] of/base: release the node correctly
-Original Message-
From: Stephen Rothwell [mailto:s...@canb.auug.org.au]
Sent: 2013年4月10日 17:03
To: Tang Yuantian-B29983
Cc: grant.lik...@secretlab.ca; devicetree-disc...@lists.ozlabs.org;
linuxppc-dev@lists.ozlabs.org; linux-ker...@vger.kernel.org;
rob.herr...@calxeda.com
Subject
Also send this patch to cpuf...@vger.kernel.org and linux...@vger.kernel.org
And better to rebase it on
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git
Thanks,
Yuantian
-Original Message-
From: Linuxppc-dev [mailto:linuxppc-dev-
-Original Message-
From: cpufreq-ow...@vger.kernel.org [mailto:cpufreq-ow...@vger.kernel.org]
On Behalf Of Viresh Kumar
Sent: 2013年3月30日 21:52
To: Tang Yuantian-B29983
Cc: Rafael J. Wysocki; cpuf...@vger.kernel.org; Linux PM list; linuxppc-
d...@lists.ozlabs.org; Li Yang-R58472
+static int corenet_cpufreq_cpu_init(struct cpufreq_policy *policy) {
+ unsigned int cpu = policy-cpu;
+ struct device_node *np;
+ int i, count;
+ struct clk *clk;
+ struct cpufreq_frequency_table *table;
+ struct cpu_data *data;
+
+ np =
-Original Message-
From: Viresh Kumar [mailto:viresh.ku...@linaro.org]
Sent: 2013年3月29日 11:17
To: Tang Yuantian-B29983
Cc: r...@sisk.pl; cpuf...@vger.kernel.org; linux...@vger.kernel.org;
linuxppc-dev@lists.ozlabs.org; Li Yang-R58472
Subject: Re: [PATCH 2/2 v2] cpufreq: Add
+ return ret;
+
+ pr_info(Freescale PowerPC corenet CPU frequency scaling driver\n);
+
+ return ret;
+}
+
+static void __exit ppc_corenet_cpufreq_exit(void) {
+ cpufreq_unregister_driver(ppc_corenet_cpufreq_driver);
+}
+
Subject: Re: [PATCH][V2] powerpc: remove the PPC_CLOCK dependency
On Mar 6, 2013, at 3:16 AM, yuantian.t...@freescale.com
yuantian.t...@freescale.com wrote:
From: Tang Yuantian yuantian.t...@freescale.com
config FSL_SOC and CPM do not really depend on PPC_CLOCK. So remove it.
Hi Cedric MAUSSIRE,
P2020RDB-PCA Board gets supported since kernel 3.3 in mainline code.
Are you sure the board works on kernel 2.6.35?
Regards,
Yuantian
From: linuxppc-dev-bounces+b29983=freescale@lists.ozlabs.org
[mailto:linuxppc-dev-bounces+b29983=freescale@lists.ozlabs.org] On
I'm curious how fsl_pq_mdio_probe returns successfully when probing the
phys on the first pass (mdio@24000). I don't have a P1024 to test with,
but I believe it has the same ETSEC configuration as the P1010 that I
work with.
Inside the fsl_pq_mdio_probe routine (fsl_pq_mdio.c), a
P1020rdb has vitesse-7385 switch.
I'm talking about the SoC, not the board.
fsl/p1020si-post.dtsi can be used for both boards.
What are you basing this on? Has someone looked over both manuals in
detail and concluded that every device described is 100% compatible?
I ported this
On 01/09/2012 02:37 AM, b29...@freescale.com wrote:
+/include/ p1024rdb.dtsi
+/include/ fsl/p1020si-post.dtsi
Is p1024 100% software-compatible with p1020?
They have different manuals...
-Scott
P1020rdb has vitesse-7385 switch.
fsl/p1020si-post.dtsi can be used for both boards.
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