Hi,
Subject: [PATCH V1] ASoC: fsl_ssi: refine ipg clock usage in this module
Move the ipg clock enable and disable operation to startup and shutdown,
that is only enable ipg clock when ssi is working. we don't need to enable
ipg clock in probe.
Another register accessing need the ipg
Subject: Re: [alsa-devel] [PATCH V1 1/3] ASoC: fsl: Kconfig: remove dependence
of SND_IMX_SOC for SND_SOC_IMX_PCM_DMA
On Mon, Aug 18, 2014 at 06:52:46PM +0200, Lars-Peter Clausen wrote:
On 08/18/2014 10:38 AM, Shengjiu Wang wrote:
Build kernel with SND_SOC_IMC_PCM_DMA=m SND_IMX_SOC=n
Lars-Peter Clausen Arnd
The purpose of Arnd's patch is same with me, which is to resolve the build
error when SND_SOC_IMX_PCM_DMA=m SND_SOC_FSL_SSI/SAI/ESAI/SPDIF=y, the
error is undefined reference to `imx_pcm_dma_init'.
But Arnd's patch didn't involve this situation that
How about the following :
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 5ae777a..d42f18c 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -15,7 +15,7 @@ config SND_SOC_FSL_ASRC
config SND_SOC_FSL_SAI
tristate Synchronous Audio Interface (SAI) module
;
Chen Guangyu-B42378
Subject: [PATCH 0/2] ASoC: fsl_sai: Two bug fixes for fsl_sai driver
Nicolin Chen (2):
ASoC: fsl_sai: Reset FIFOs after disabling TE/RE
ASoC: fsl_sai: Fix incorrect register writing in fsl_sai_isr()
Yes, they are all looks good to me.
Signed-off-by: Xiubo Li li.xi
-by: Nicolin Chen guangyu.c...@freescale.com
CC: Xiubo Li li.xi...@freescale.com
Acked-by: Shawn Guo shawn@linaro.org
---
@Xiubo
Even though you've tested it before, I'd still like to wait for your test
result to this newer version.
Changelog
v4:
* Merged into single patch.
* Fixed bus
and big noise with WM8962.
Thus this patch corrects the BCP settings for all the formats here to fix
the nosie issue.
Signed-off-by: Nicolin Chen guangyu.c...@freescale.com
---
Good catch.
Acked-by: Xiubo Li li.xi...@freescale.com
Thanks,
--
BRs,
Xiubo
sound/soc/fsl/fsl_sai.c | 8
Is that possible for you to test those two clock patches for fsl_sai?
I think most of us are waiting for your reply to it. And I'd really
like to move on to append clock dividing code into the driver so both
of vybrid and imx can easily enable the DAI master mode.
Certainly, I will
the clock options properly.
Otherwise it look good to me.
After this:
Acked-by: Xiubo Li li.xi...@freescale.com
Thanks,
Brs,
Xiubo
+ sai-sai_clk = devm_clk_get(pdev-dev, sai);
+ if (IS_ERR(sai-sai_clk)) {
+ dev_err(pdev-dev, failed to get sai clock\n
:
52.3.1.3 Bus clock
The bus clock is used by the control and configuration registers and to
generate synchronous interrupts and DMA requests.
Thanks,
Nicolin
Otherwise it look good to me.
After this:
Acked-by: Xiubo Li li.xi...@freescale.com
Thanks,
Brs,
Xiubo
Subject: Re: [PATCH v2 2/2] ARM: dts: Append clock bindings for sai2 on VF610
platform
Hi Shawn,
Thanks for the comments, but...
On Wed, Apr 02, 2014 at 09:03:04PM +0800, Shawn Guo wrote:
On Wed, Apr 02, 2014 at 06:10:20PM +0800, Nicolin Chen wrote:
Since we added fours clock
| aplay
d) (aplay test2.wav ); sleep 1; arecord -r44100 -c2 -fS16_LE test.wav -d1
e) (arecord -r44100 -c2 -fS16_LE test.wav -d5 ); sleep 1; aplay test.wav -d1
Signed-off-by: Nicolin Chen guangyu.c...@freescale.com
---
I have test it on my Vybird board.
Acked-by: Xiubo Li li.xi...@freescale.com
@@ -1752,6 +1793,22 @@ static int fsl_diu_probe(struct platform_device *pdev)
goto error;
}
+ if (!diu_ops.set_pixel_clock) {
+ data-pixelclk_reg = of_iomap(np, 1);
+ if (!data-pixelclk_reg) {
+ dev_err(pdev-dev, Cannot
+ regmap_read(sai-regmap, FSL_SAI_TCSR, xcsr);
+ regmap_write(sai-regmap, FSL_SAI_TCSR, xcsr);
+
+ if (xcsr FSL_SAI_CSR_WSF)
+ dev_dbg(dev, isr: Start of Tx word detected\n);
+
+ if (xcsr FSL_SAI_CSR_SEF)
+ dev_dbg(dev, isr: Tx Frame sync error
On Thu, Mar 27, 2014 at 10:13:48AM +0800, Xiubo Li-B47053 wrote:
+ regmap_read(sai-regmap, FSL_SAI_TCSR, xcsr);
+ regmap_write(sai-regmap, FSL_SAI_TCSR, xcsr);
+
+ if (xcsr FSL_SAI_CSR_WSF)
+ dev_dbg(dev, isr: Start of Tx word detected\n);
+
+ if (xcsr
Subject: Re: [PATCH] ASoC: fsl_sai: Add isr to deal with error flag
On Thu, Mar 27, 2014 at 10:53:50AM +0800, Xiubo Li-B47053 wrote:
On Thu, Mar 27, 2014 at 10:13:48AM +0800, Xiubo Li-B47053 wrote:
+ regmap_read(sai-regmap, FSL_SAI_TCSR, xcsr);
+ regmap_write(sai-regmap,
+ if (xcsr FSL_SAI_CSR_FWF)
+ dev_dbg(dev, isr: Enabled transmit FIFO is empty\n);
+
+ if (xcsr FSL_SAI_CSR_FRF)
+ dev_dbg(dev, isr: Transmit FIFO watermark has been
reached\n);
+
While are these ones really needed to clear
So let's just ignore the clearance of these bits in isr().
+
SAI Transmit Control Register (I2S1_TCSR) : 32 : R/W : _h
I'm talking about FWF and FRF bits, not TCSR as a register.
-
I have checked in the Vybrid and LS1 SoC datasheets, and they are all the
Same
Hi Mark,
Subject: Re: [PATCH] ASoC: fsl_sai: Fix one bug for hardware limitation.
On Thu, Dec 26, 2013 at 10:57:22AM +0800, Xiubo Li wrote:
This is maybe one bug or a limitation of the hardware that the {T,R}CR2's
Synchronous Mode bits must be set as late as possible, or the SAI device
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