[PATCH v2 06/10] KVM: PPC: add giveup_ext() hook for PPC KVM ops

From: Simon Guo Currently HV will save math regs(FP/VEC/VSX) when trap into host. But PR KVM will only save math regs when qemu task switch out of CPU, or when returning from qemu code. To emulate FP/VEC/VSX mmio load, PR KVM need to make sure that math regs were

[PATCH v2 07/10] KVM: PPC: reimplement LOAD_FP/STORE_FP instruction mmio emulation with analyse_intr() input

From: Simon Guo This patch reimplements LOAD_FP/STORE_FP instruction MMIO emulation with analyse_intr() input. It utilizes the FPCONV/UPDATE properties exported by analyse_instr() and invokes kvmppc_handle_load(s)/kvmppc_handle_store() accordingly. For FP store MMIO

[PATCH v2 05/10] KVM: PPC: reimplement non-SIMD LOAD/STORE instruction mmio emulation with analyse_intr() input

From: Simon Guo This patch reimplements non-SIMD LOAD/STORE instruction MMIO emulation with analyse_intr() input. It utilizes the BYTEREV/UPDATE/SIGNEXT properties exported by analyse_instr() and invokes kvmppc_handle_load(s)/kvmppc_handle_store() accordingly. It also

[PATCH v2 04/10] KVM: PPC: add KVMPPC_VSX_COPY_WORD_LOAD_DUMP type support for mmio emulation

From: Simon Guo Some VSX instruction like lxvwsx will splat word into VSR. This patch adds VSX copy type KVMPPC_VSX_COPY_WORD_LOAD_DUMP to support this. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras ---

[PATCH v2 03/10] KVM: PPC: Fix a mmio_host_swabbed uninitialized usage issue when VMX store

From: Simon Guo When KVM emulates VMX store, it will invoke kvmppc_get_vmx_data() to retrieve VMX reg val. kvmppc_get_vmx_data() will check mmio_host_swabbed to decide which double word of vr[] to be used. But the mmio_host_swabbed can be uninitiazed during VMX store

[PATCH v2 02/10] KVM: PPC: mov nip/ctr/lr/xer registers to pt_regs in kvm_vcpu_arch

From: Simon Guo This patch moves nip/ctr/lr/xer registers from scattered places in kvm_vcpu_arch to pt_regs structure. cr register is "unsigned long" in pt_regs and u32 in vcpu->arch. It will need more consideration and may move in later patches. Signed-off-by: Simon

[PATCH v2 01/10] KVM: PPC: add pt_regs into kvm_vcpu_arch and move vcpu->arch.gpr[] into it

From: Simon Guo Current regs are scattered at kvm_vcpu_arch structure and it will be more neat to organize them into pt_regs structure. Also it will enable reimplementation of MMIO emulation code with analyse_instr() later. Signed-off-by: Simon Guo

[PATCH v2 00/10] KVM: PPC: reimplement mmio emulation with analyse_instr()

From: Simon Guo We already have analyse_instr() which analyzes instructions for the instruction type, size, addtional flags, etc. What kvmppc_emulate_loadstore() did is somehow duplicated and it will be good to utilize analyse_instr() to reimplement the code. The

[PATCH 11/11] KVM: PPC: reconstruct LOAD_VSX/STORE_VSX instruction mmio emulation with analyse_intr() input

From: Simon Guo This patch reconstructs LOAD_VSX/STORE_VSX instruction MMIO emulation with analyse_intr() input. It utilizes VSX_FPCONV/VSX_SPLAT/SIGNEXT exported by analyse_instr() and handle accordingly. When emulating VSX store, the VSX reg will need to be flushed so

[PATCH 10/11] KVM: PPC: reconstruct LOAD_VMX/STORE_VMX instruction mmio emulation with analyse_intr() input

From: Simon Guo This patch reconstructs LOAD_VMX/STORE_VMX instruction MMIO emulation with analyse_intr() input. When emulating the store, the VMX reg will need to be flushed so that the right reg val can be retrieved before writing to IO MEM. Suggested-by: Paul

[PATCH 09/11] KVM: PPC: reconstruct LOAD_FP/STORE_FP instruction mmio emulation with analyse_intr() input

From: Simon Guo This patch reconstructs LOAD_FP/STORE_FP instruction MMIO emulation with analyse_intr() input. It utilizes the FPCONV/UPDATE properties exported by analyse_instr() and invokes kvmppc_handle_load(s)/kvmppc_handle_store() accordingly. The FP regs need to

[PATCH 08/11] KVM: PPC: add giveup_ext() hook for PPC KVM ops

From: Simon Guo Currently HV will save math regs(FP/VEC/VSX) when trap into host. But PR KVM will only save math regs when qemu task switch out of CPU. To emulate FP/VEC/VSX load, PR KVM need to flush math regs firstly and then be able to update saved VCPU FPR/VEC/VSX

[PATCH 07/11] KVM: PPC: reconstruct non-SIMD LOAD/STORE instruction mmio emulation with analyse_intr() input

From: Simon Guo This patch reconstructs non-SIMD LOAD/STORE instruction MMIO emulation with analyse_intr() input. It utilizes the BYTEREV/UPDATE/SIGNEXT properties exported by analyse_instr() and invokes kvmppc_handle_load(s)/kvmppc_handle_store() accordingly. It also

[PATCH 06/11] KVM: PPC: add KVMPPC_VSX_COPY_WORD_LOAD_DUMP type support for mmio emulation

From: Simon Guo Some VSX instruction like lxvwsx will splat word into VSR. This patch adds VSX copy type KVMPPC_VSX_COPY_WORD_LOAD_DUMP to support this. Signed-off-by: Simon Guo --- arch/powerpc/include/asm/kvm_host.h | 1 +

[PATCH 05/11] KVM: PPC: add GPR RA update skeleton for MMIO emulation

From: Simon Guo To optimize kvm emulation code with analyse_instr, adds new mmio_update_ra flag to aid with GPR RA update. This patch arms RA update at load/store emulation path for both qemu mmio emulation or coalesced mmio emulation. Signed-off-by: Simon Guo

[PATCH 04/11] KVM: PPC: fix incorrect element_size for stxsiwx in analyse_instr

From: Simon Guo stwsiwx will place contents of word element 1 of VSR into word storage of EA. So the element size of stwsiwx should be 4. This patch correct the size from 8 to 4. Signed-off-by: Simon Guo --- arch/powerpc/lib/sstep.c | 2 +- 1

[PATCH 03/11] KVM: PPC: Fix a mmio_host_swabbed uninitialized usage issue when VMX store

From: Simon Guo When KVM emulates VMX store, it will invoke kvmppc_get_vmx_data() to retrieve VMX reg val. kvmppc_get_vmx_data() will check mmio_host_swabbed to decide which double word of vr[] to be used. But the mmio_host_swabbed can be uninitiazed during VMX store

[PATCH 01/11] KVM: PPC: add pt_regs into kvm_vcpu_arch and move vcpu->arch.gpr[] into it

From: Simon Guo Current regs are scattered at kvm_vcpu_arch structure and it will be more neat to organize them into pt_regs structure. Also it will enable reconstruct MMIO emulation code with analyse_instr() later. Signed-off-by: Simon Guo

[PATCH 02/11] KVM: PPC: mov nip/ctr/lr/xer registers to pt_regs in kvm_vcpu_arch

From: Simon Guo This patch moves nip/ctr/lr/xer registers from scattered places in kvm_vcpu_arch to pt_regs structure. cr register is "unsigned long" in pt_regs and u32 in vcpu->arch. It will need more consideration and may move in later patches. Signed-off-by: Simon

[PATCH 00/11] KVM: PPC: reconstruct mmio emulation with analyse_instr()

From: Simon Guo We already have analyse_instr() which analyzes instructions for the instruction type, size, addtional flags, etc. What kvmppc_emulate_loadstore() did is somehow duplicated and it will be good to utilize analyse_instr() to reconstruct the code. The

[PATCH] PCI/hotplug: ppc: correct a php_slot usage after free

From: Simon Guo In pnv_php_unregister_one(), pnv_php_put_slot() might kfree php_slot structure. But there is pci_hp_deregister() after that with php_slot reference. This patch moves pnv_php_put_slot() to the end of function. Signed-off-by: Simon Guo

[PATCH] KVM: surround kvm_arch_vcpu_async_ioctl() with #ifdef

From: Simon Guo Although CONFIG_HAVE_KVM_VCPU_ASYNC_IOCTL is usually on, logically kvm_arch_vcpu_async_ioctl() definition should be wrapped with CONFIG_HAVE_KVM_VCPU_ASYNC_IOCTL #ifdef. This patch adds the #ifdef surround. Signed-off-by: Simon Guo

[PATCH v2 30/30] KVM: PPC: Book3S PR: enable kvmppc_get/set_one_reg_pr() for HTM registers

From: Simon Guo We need to migrate PR KVM during transaction and qemu will use kvmppc_get_one_reg_pr()/kvmppc_set_one_reg_pr() APIs to get/set transaction checkpoint state. This patch adds support for that. So far PPC PR qemu doesn't fully function for migration but the

[PATCH v2 29/30] KVM: PPC: add KVM_SET_ONE_REG/KVM_GET_ONE_REG to async ioctl

From: Simon Guo In both HV/PR KVM, the KVM_SET_ONE_REG/KVM_GET_ONE_REG ioctl should be able to perform without load vcpu. This patch adds KVM_SET_ONE_REG/KVM_GET_ONE_REG implementation to async ioctl function. Signed-off-by: Simon Guo ---

[PATCH v2 28/30] KVM: PPC: remove load/put vcpu for KVM_GET_REGS/KVM_SET_REGS

From: Simon Guo In both HV/PR KVM, the KVM_SET_REGS/KVM_GET_REGS ioctl should be able to perform without load vcpu. This patch adds KVM_SET_ONE_REG/KVM_GET_ONE_REG implementation to async ioctl function. Due to the vcpu mutex locking/unlock has been moved out of

[PATCH v2 27/30] KVM: PPC: remove load/put vcpu for KVM_GET/SET_ONE_REG ioctl

From: Simon Guo Due to the vcpu mutex locking/unlock has been moved out of vcpu_load() /vcpu_put(), KVM_GET_ONE_REG and KVM_SET_ONE_REG doesn't need to do ioctl with loading vcpu anymore. This patch removes vcpu_load()/vcpu_put() from KVM_GET_ONE_REG and KVM_SET_ONE_REG

[PATCH v2 26/30] KVM: PPC: move vcpu_load/vcpu_put down to each ioctl case in kvm_arch_vcpu_ioctl

From: Simon Guo Although we already have kvm_arch_vcpu_async_ioctl() which doesn't require ioctl to load vcpu, the sync ioctl code need to be cleaned up when CONFIG_HAVE_KVM_VCPU_ASYNC_IOCTL is not configured. This patch moves vcpu_load/vcpu_put down to each ioctl

[PATCH v2 25/30] KVM: PPC: Book3S PR: enable HTM for PR KVM for KVM_CHECK_EXTENSION ioctl

From: Simon Guo With current patch set, PR KVM now supports HTM. So this patch turns it on for PR KVM. Tested with: https://github.com/justdoitqd/publicFiles/blob/master/test_kvm_htm_cap.c Signed-off-by: Simon Guo ---

[PATCH v2 24/30] KVM: PPC: Book3S PR: Support TAR handling for PR KVM HTM.

From: Simon Guo Currently guest kernel doesn't handle TAR fac unavailable and it always runs with TAR bit on. PR KVM will lazily enable TAR. TAR is not a frequent-use reg and it is not included in SVCPU struct. Due to the above, the checkpointed TAR val might be a bogus

[PATCH v2 22/30] KVM: PPC: Book3S PR: add emulation for tabort. for privilege guest

From: Simon Guo Currently privilege guest will be run with TM disabled. Although the privilege guest cannot initiate a new transaction, it can use tabort to terminate its problem state's transaction. So it is still necessary to emulate tabort. for privilege guest. This

[PATCH v2 23/30] KVM: PPC: Book3S PR: add guard code to prevent returning to guest with PR=0 and Transactional state

From: Simon Guo Currently PR KVM doesn't support transaction memory at guest privilege state. This patch adds a check at setting guest msr, so that we can never return to guest with PR=0 and TS=0b10. A tabort will be emulated to indicate this and fail transaction

[PATCH v2 21/30] KVM: PPC: Book3S PR: add emulation for trechkpt in PR KVM.

From: Simon Guo This patch adds host emulation when guest PR KVM executes "trechkpt.", which is a privileged instruction and will trap into host. We firstly copy vcpu ongoing content into vcpu tm checkpoint content, then perform kvmppc_restore_tm_pr() to do trechkpt.

[PATCH v2 20/30] KVM: PPC: Book3S PR: adds emulation for treclaim.

From: Simon Guo This patch adds support for "treclaim." emulation when PR KVM guest executes treclaim. and traps to host. We will firstly doing treclaim. and save TM checkpoint. Then it is necessary to update vcpu current reg content with checkpointed vals. When rfid

[PATCH v2 18/30] KVM: PPC: Book3S PR: always fail transaction in guest privilege state

From: Simon Guo Currently kernel doesn't use transaction memory. And there is an issue for privilege guest that: tbegin/tsuspend/tresume/tabort TM instructions can impact MSR TM bits without trap into PR host. So following code will lead to a false mfmsr result:

[PATCH v2 19/30] KVM: PPC: Book3S PR: enable NV reg restore for reading TM SPR at guest privilege state

From: Simon Guo Currently kvmppc_handle_fac() will not update NV GPRs and thus it can return with GUEST_RESUME. However PR KVM guest always disables MSR_TM bit at privilege state. If PR privilege guest are trying to read TM SPRs, it will trigger TM facility unavailable

[PATCH v2 17/30] KVM: PPC: Book3S PR: make mtspr/mfspr emulation behavior based on active TM SPRs

From: Simon Guo The mfspr/mtspr on TM SPRs(TEXASR/TFIAR/TFHAR) are non-privileged instructions and can be executed at PR KVM guest without trapping into host in problem state. We only emulate mtspr/mfspr texasr/tfiar/tfhar at guest PR=0 state. When we are emulating

[PATCH v2 16/30] KVM: PPC: Book3S PR: add math support for PR KVM HTM

From: Simon Guo The math registers will be saved into vcpu->arch.fp/vr and corresponding vcpu->arch.fp_tm/vr_tm area. We flush or giveup the math regs into vcpu->arch.fp/vr before saving transaction. After transaction is restored, the math regs will be loaded back into

[PATCH v2 15/30] KVM: PPC: Book3S PR: add transaction memory save/restore skeleton for PR KVM

From: Simon Guo The transaction memory checkpoint area save/restore behavior is triggered when VCPU qemu process is switching out/into CPU. ie. at kvmppc_core_vcpu_put_pr() and kvmppc_core_vcpu_load_pr(). MSR TM active state is determined by TS bits: active:

[PATCH v2 14/30] KVM: PPC: Book3S PR: add kvmppc_save/restore_tm_sprs() APIs

From: Simon Guo This patch adds 2 new APIs kvmppc_save_tm_sprs()/kvmppc_restore_tm_sprs() for the purpose of TEXASR/TFIAR/TFHAR save/restore. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras ---

[PATCH v2 13/30] KVM: PPC: Book3S PR: adds new kvmppc_copyto_vcpu_tm/kvmppc_copyfrom_vcpu_tm API for PR KVM.

From: Simon Guo This patch adds 2 new APIs: kvmppc_copyto_vcpu_tm() and kvmppc_copyfrom_vcpu_tm(). These 2 APIs will be used to copy from/to TM data between VCPU_TM/VCPU area. PR KVM will use these APIs for treclaim. or trchkpt. emulation. Signed-off-by: Simon Guo

[PATCH v2 12/30] KVM: PPC: Book3S PR: prevent TS bits change in kvmppc_interrupt_pr()

From: Simon Guo PR KVM host usually equipped with enabled TM in its host MSR value, and with non-transactional TS value. When a guest with TM active traps into PR KVM host, the rfid at the tail of kvmppc_interrupt_pr() will try to switch TS bits from S0 (Suspended & TM

[PATCH v2 11/30] KVM: PPC: Book3S PR: implement RFID TM behavior to suppress change from S0 to N0

From: Simon Guo Accordingly to ISA specification for RFID, in MSR TM disabled and TS suspended state(S0), if the target MSR is TM disabled and TS state is inactive(N0), rfid should suppress this update. This patch make RFID emulation of PR KVM to be consistent with

[PATCH v2 10/30] KVM: PPC: Book3S PR: Sync TM bits to shadow msr for problem state guest

From: Simon Guo MSR TS bits can be modified with non-privileged instruction like tbegin./tend. That means guest can change MSR value "silently" without notifying host. It is necessary to sync the TM bits to host so that host can calculate shadow msr correctly. note

[PATCH v2 09/30] KVM: PPC: Book3S PR: PR KVM pass through MSR TM/TS bits to shadow_msr.

From: Simon Guo PowerPC TM functionality needs MSR TM/TS bits support in hardware level. Guest TM functionality can not be emulated with "fake" MSR (msr in magic page) TS bits. This patch syncs TM/TS bits in shadow_msr with the MSR value in magic page, so that the MSR

[PATCH v2 08/30] KVM: PPC: Book3S PR: In PR KVM suspends Transactional state when inject an interrupt.

From: Simon Guo This patch simulates interrupt behavior per Power ISA while injecting interrupt in PR KVM: - When interrupt happens, transactional state should be suspended. kvmppc_mmu_book3s_64_reset_msr() will be invoked when injecting an interrupt. This patch

[PATCH v2 07/30] KVM: PPC: Book3S PR: add C function wrapper for _kvmppc_save/restore_tm()

From: Simon Guo Currently _kvmppc_save/restore_tm() APIs can only be invoked from assembly function. This patch adds C function wrappers for them so that they can be safely called from C function. Signed-off-by: Simon Guo ---

[PATCH v2 06/30] KVM: PPC: Book3S PR: turn on FP/VSX/VMX MSR bits in kvmppc_save_tm()

From: Simon Guo kvmppc_save_tm() invokes store_fp_state/store_vr_state(). So it is mandatory to turn on FP/VSX/VMX MSR bits for its execution, just like what kvmppc_restore_tm() did. Previsouly HV KVM has turned the bits on outside of function kvmppc_save_tm(). Now we

[PATCH v2 05/30] KVM: PPC: Book3S PR: add new parameter (guest MSR) for kvmppc_save_tm()/kvmppc_restore_tm()

From: Simon Guo HV KVM and PR KVM need different MSR source to indicate whether treclaim. or trecheckpoint. is necessary. This patch add new parameter (guest MSR) for these kvmppc_save_tm/ kvmppc_restore_tm() APIs: - For HV KVM, it is VCPU_MSR - For PR KVM, it is

[PATCH v2 04/30] KVM: PPC: Book3S PR: Move kvmppc_save_tm/kvmppc_restore_tm to separate file

From: Simon Guo It is a simple patch just for moving kvmppc_save_tm/kvmppc_restore_tm() functionalities to tm.S. There is no logic change. The reconstruct of those APIs will be done in later patches to improve readability. It is for preparation of reusing those APIs on

[PATCH v2 03/30] powerpc: export tm_enable()/tm_disable/tm_abort() APIs

From: Simon Guo This patch exports tm_enable()/tm_disable/tm_abort() APIs, which will be used for PR KVM transaction memory logic. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras ---

[PATCH v2 01/30] powerpc: export symbol msr_check_and_set().

From: Simon Guo PR KVM will need to reuse msr_check_and_set(). This patch exports this API for reuse. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras --- arch/powerpc/kernel/process.c | 1 + 1 file changed, 1

[PATCH v2 02/30] powerpc: add TEXASR related macros

From: Simon Guo This patches add some macros for CR0/TEXASR bits so that PR KVM TM logic(tbegin./treclaim./tabort.) can make use of them later. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras ---

[PATCH v2 00/30] KVM: PPC: Book3S PR: Transaction memory support on PR KVM

From: Simon Guo In current days, many OS distributions have utilized transaction memory functionality. In PowerPC, HV KVM supports TM. But PR KVM does not. The drive for the transaction memory support of PR KVM is the openstack Continuous Integration testing - They runs

[PATCH] KVM: PPC: Book3S PR: close a race window when SVCPU pointer is hold before kvmppc_copy_from_svcpu()

From: Simon Guo commit 40fdd8c88c4a ("KVM: PPC: Book3S: PR: Make svcpu -> vcpu store preempt savvy") and commit 3d3319b45eea ("KVM: PPC: Book3S: PR: Enable interrupts earlier") is trying to turns on preemption early when return into highmem guest exit handler. However

[PATCH 26/26] KVM: PPC: Book3S PR: enable HTM for PR KVM for KVM_CHECK_EXTENSION ioctl

From: Simon Guo With current patch set, PR KVM now supports HTM. So this patch turns it on for PR KVM. Tested with: https://github.com/justdoitqd/publicFiles/blob/master/test_kvm_htm_cap.c Signed-off-by: Simon Guo ---

[PATCH 25/26] KVM: PPC: Book3S PR: Support TAR handling for PR KVM HTM.

From: Simon Guo Currently guest kernel doesn't handle TAR fac unavailable and it always runs with TAR bit on. PR KVM will lazily enable TAR. TAR is not a frequent-use reg and it is not included in SVCPU struct. To make it work for transaction memory at PR KVM: 1).

[PATCH 24/26] KVM: PPC: Book3S PR: add guard code to prevent returning to guest with PR=0 and Transactional state

From: Simon Guo Currently PR KVM doesn't support transaction memory at guest privilege state. This patch adds a check at setting guest msr, so that we can never return to guest with PR=0 and TS=0b10. A tabort will be emulated to indicate this and fail transaction

[PATCH 23/26] KVM: PPC: Book3S PR: add emulation for tabort. for privilege guest

From: Simon Guo Currently privilege guest will be run with TM disabled. Although the privilege guest cannot initiate a new transaction, it can use tabort to terminate its problem state's transaction. So it is still necessary to emulate tabort. for privilege guest. This

[PATCH 22/26] KVM: PPC: Book3S PR: add emulation for trechkpt in PR KVM.

From: Simon Guo This patch adds host emulation when guest PR KVM executes "trechkpt.", which is a privileged instruction and will trap into host. We firstly copy vcpu ongoing content into vcpu tm checkpoint content, then perform kvmppc_restore_tm_pr() to do trechkpt.

[PATCH 21/26] KVM: PPC: Book3S PR: adds emulation for treclaim.

From: Simon Guo This patch adds support for "treclaim." emulation when PR KVM guest executes treclaim. and traps to host. We will firstly doing treclaim. and save TM checkpoint and doing treclaim. Then it is necessary to update vcpu current reg content with checkpointed

[PATCH 20/26] KVM: PPC: Book3S PR: enable NV reg restore for reading TM SPR at guest privilege state

From: Simon Guo Currently kvmppc_handle_fac() will not update NV GPRs and thus it can return with GUEST_RESUME. However PR KVM guest always disables MSR_TM bit at privilege state. If PR privilege guest are trying to read TM SPRs, it will trigger TM facility unavailable

[PATCH 19/26] KVM: PPC: Book3S PR: always fail transaction in guest privilege state

From: Simon Guo Currently kernel doesn't use transaction memory. And there is an issue for privilege guest that: tbegin/tsuspend/tresume/tabort TM instructions can impact MSR TM bits without trap into PR host. So following code will lead to a false mfmsr result:

[PATCH 18/26] KVM: PPC: Book3S PR: make mtspr/mfspr emulation behavior based on active TM SPRs

From: Simon Guo The mfspr/mtspr on TM SPRs(TEXASR/TFIAR/TFHAR) are non-privileged instructions and can be executed at PR KVM guest without trapping into host in problem state. We only emulate mtspr/mfspr texasr/tfiar/tfhar at guest PR=0 state. When we are emulating

[PATCH 17/26] KVM: PPC: Book3S PR: add math support for PR KVM HTM

From: Simon Guo The math registers will be saved into vcpu->arch.fp/vr and corresponding vcpu->arch.fp_tm/vr_tm area. We flush or giveup the math regs into vcpu->arch.fp/vr before saving transaction. After transaction is restored, the math regs will be loaded back into

[PATCH 16/26] KVM: PPC: Book3S PR: add transaction memory save/restore skeleton for PR KVM

From: Simon Guo The transaction memory checkpoint area save/restore behavior is triggered when VCPU qemu process is switching out/into CPU. ie. at kvmppc_core_vcpu_put_pr() and kvmppc_core_vcpu_load_pr(). MSR TM active state is determined by TS bits: active:

[PATCH 15/26] KVM: PPC: Book3S PR: add kvmppc_save/restore_tm_sprs() APIs

From: Simon Guo This patch adds 2 new APIs kvmppc_save_tm_sprs()/kvmppc_restore_tm_sprs() for the purpose of TEXASR/TFIAR/TFHAR save/restore. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras ---

[PATCH 14/26] KVM: PPC: Book3S PR: export tm_enable()/tm_disable/tm_abort() APIs

From: Simon Guo This patch exports tm_enable()/tm_disable/tm_abort() APIs, which will be used for PR KVM transaction memory logic. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras ---

[PATCH 13/26] KVM: PPC: Book3S PR: adds new kvmppc_copyto_vcpu_tm/kvmppc_copyfrom_vcpu_tm API for PR KVM.

From: Simon Guo This patch adds 2 new APIs: kvmppc_copyto_vcpu_tm() and kvmppc_copyfrom_vcpu_tm(). These 2 APIs will be used to copy from/to TM data between VCPU_TM/VCPU area. PR KVM will use these APIs for treclaim. or trchkpt. emulation. Signed-off-by: Simon Guo

[PATCH 12/26] powerpc: export symbol msr_check_and_set().

From: Simon Guo PR KVM will need to reuse msr_check_and_set(). This patch exports this API for reuse. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras --- arch/powerpc/kernel/process.c | 1 + 1 file changed, 1

[PATCH 11/26] KVM: PPC: Book3S PR: prevent TS bits change in kvmppc_interrupt_pr()

From: Simon Guo PR KVM host usually equipped with enabled TM in its host MSR value, and with non-transactional TS value. When a guest with TM active traps into PR KVM host, the rfid at the tail of kvmppc_interrupt_pr() will try to switch TS bits from S0 (Suspended & TM

[PATCH 10/26] KVM: PPC: Book3S PR: set MSR HV bit accordingly for PPC970 and others.

From: Simon Guo Apple G5 machines(PPC970/FX/GX/MP) have supervisor mode disabled and MSR HV bit is forced into 1. We should follow this in PR KVM guest. This patch set MSR HV=1 for G5 machines and HV=0 for others on PR KVM guest. Signed-off-by: Simon Guo

[PATCH 09/26] KVM: PPC: Book3S PR: implement RFID TM behavior to suppress change from S0 to N0

From: Simon Guo Accordingly to ISA specification for RFID, in MSR TM disabled and TS suspended state(S0), if the target MSR is TM disabled and TS state is inactive(N0), rfid should suppress this update. This patch make RFID emulation of PR KVM to be consistent with

[PATCH 08/26] KVM: PPC: Book3S PR: Sync TM bits to shadow msr for problem state guest

From: Simon Guo MSR TS bits can be modified with non-privileged instruction like tbegin./tend. That means guest can change MSR value "silently" without notifying host. It is necessary to sync the TM bits to host so that host can calculate shadow msr correctly. note

[PATCH 07/26] KVM: PPC: Book3S PR: add TEXASR related macros

From: Simon Guo This patches add some macros for CR0/TEXASR bits so that PR KVM TM logic(tbegin./treclaim./tabort.) can make use of them later. Signed-off-by: Simon Guo --- arch/powerpc/include/asm/reg.h | 21 -

[PATCH 06/26] KVM: PPC: Book3S PR: PR KVM pass through MSR TM/TS bits to shadow_msr.

From: Simon Guo PowerPC TM functionality needs MSR TM/TS bits support in hardware level. Guest TM functionality can not be emulated with "fake" MSR (msr in magic page) TS bits. This patch syncs TM/TS bits in shadow_msr with the MSR value in magic page, so that the MSR

[PATCH 05/26] KVM: PPC: Book3S PR: In PR KVM suspends Transactional state when inject an interrupt.

From: Simon Guo This patch simulates interrupt behavior per Power ISA while injecting interrupt in PR KVM: - When interrupt happens, transactional state should be suspended. kvmppc_mmu_book3s_64_reset_msr() will be invoked when injecting an interrupt. This patch

[PATCH 04/26] KVM: PPC: Book3S PR: add C function wrapper for _kvmppc_save/restore_tm()

From: Simon Guo Currently _kvmppc_save/restore_tm() APIs can only be invoked from assembly function. This patch adds C function wrappers for them so that they can be safely called from C function. Signed-off-by: Simon Guo ---

[PATCH 03/26] KVM: PPC: Book3S PR: turn on FP/VSX/VMX MSR bits in kvmppc_save_tm()

From: Simon Guo kvmppc_save_tm() invokes store_fp_state/store_vr_state(). So it is mandatory to turn on FP/VSX/VMX MSR bits for its execution, just like what kvmppc_restore_tm() did. Previsouly HV KVM has turned the bits on outside of function kvmppc_save_tm(). Now we

[PATCH 02/26] KVM: PPC: Book3S PR: add new parameter (guest MSR) for kvmppc_save_tm()/kvmppc_restore_tm()

From: Simon Guo HV KVM and PR KVM need different MSR source to indicate whether treclaim. or trecheckpoint. is necessary. This patch add new parameter (guest MSR) for these kvmppc_save_tm/ kvmppc_restore_tm() APIs: - For HV KVM, it is VCPU_MSR - For PR KVM, it is

[PATCH 01/26] KVM: PPC: Book3S PR: Move kvmppc_save_tm/kvmppc_restore_tm to separate file

From: Simon Guo It is a simple patch just for moving kvmppc_save_tm/kvmppc_restore_tm() functionalities to tm.S. There is no logic change. The reconstruct of those APIs will be done in later patches to improve readability. It is for preparation of reusing those APIs on

[PATCH 00/26] KVM: PPC: Book3S PR: Transaction memory support on PR KVM

From: Simon Guo In current days, many OS distributions have utilized transaction memory functionality. In PowerPC, HV KVM supports TM. But PR KVM does not. The drive for the transaction memory support of PR KVM is the openstack Continuous Integration testing - They runs

[PATCH v3 3/3] powerpc:selftest update memcmp_64 selftest for VMX implementation

From: Simon Guo This patch adjust selftest memcmp_64 so that memcmp selftest can be compiled successfully. It also adds testcases for: - memcmp over 4K bytes size. - s1/s2 with different/random offset on 16 bytes boundary. - enter/exit_vmx_ops pairness. Signed-off-by:

[PATCH v3 2/3] powerpc/64: enhance memcmp() with VMX instruction for long bytes comparision

From: Simon Guo This patch add VMX primitives to do memcmp() in case the compare size exceeds 4K bytes. KSM feature can benefit from this. Test result with following test program(replace the "^>" with ""): -- ># cat

[PATCH v3 1/3] powerpc/64: Align bytes before fall back to .Lshort in powerpc64 memcmp().

From: Simon Guo Currently memcmp() 64bytes version in powerpc will fall back to .Lshort (compare per byte mode) if either src or dst address is not 8 bytes aligned. It can be opmitized in 2 situations: 1) if both addresses are with the same offset with 8 bytes boundary:

[PATCH v3 0/3] powerpc/64: memcmp() optimization

From: Simon Guo There is some room to optimize memcmp() in powerpc 64 bits version for following 2 cases: (1) Even src/dst addresses are not aligned with 8 bytes at the beginning, memcmp() can align them and go with .Llong comparision mode without fallback to .Lshort

[PATCH v2 3/3] powerpc:selftest update memcmp_64 selftest for VMX implementation

From: Simon Guo This patch adjust selftest memcmp_64 so that memcmp selftest can be compiled successfully. It also adds testcases for memcmp over 4K bytes size. Signed-off-by: Simon Guo --- .../selftests/powerpc/copyloops/asm/ppc_asm.h |

[PATCH v2 2/3] powerpc/64: enhance memcmp() with VMX instruction for long bytes comparision

From: Simon Guo This patch add VMX primitives to do memcmp() in case the compare size exceeds 4K bytes. Test result with following test program(replace the "^>" with ""): -- ># cat tools/testing/selftests/powerpc/stringloops/memcmp.c >#include >#include >#include

[PATCH v2 1/3] powerpc/64: Align bytes before fall back to .Lshort in powerpc64 memcmp().

From: Simon Guo Currently memcmp() 64bytes version in powerpc will fall back to .Lshort (compare per byte mode) if either src or dst address is not 8 bytes aligned. It can be opmitized if both addresses are with the same offset with 8 bytes boundary. memcmp() can

[PATCH v2 0/3] powerpc/64: memcmp() optimization

From: Simon Guo There is some room to optimize memcmp() in powerpc 64 bits version for following 2 cases: (1) Even src/dst addresses are not aligned with 8 bytes at the beginning, memcmp() can align them and go with .Llong comparision mode without fallback to .Lshort

[PATCH v1 3/3] powerpc:selftest update memcmp selftest according to kernel change

From: Simon Guo This patch adjust selftest files related with memcmp so that memcmp selftest can be compiled successfully. Signed-off-by: Simon Guo --- .../selftests/powerpc/copyloops/asm/ppc_asm.h | 2 +-

[PATCH v1 2/3] powerpc: enhance memcmp() with VMX instruction for long bytes comparision

From: Simon Guo This patch add VMX primitives to do memcmp() in case the compare size exceeds 4K bytes. Test result with following test program: -- tools/testing/selftests/powerpc/stringloops# cat memcmp.c int test_memcmp(const void *s1, const void *s2, size_t n);

[PATCH v1 1/3] powerpc: Align bytes before fall back to .Lshort in powerpc memcmp

From: Simon Guo Currently memcmp() in powerpc will fall back to .Lshort (compare per byte mode) if either src or dst address is not 8 bytes aligned. It can be opmitized if both addresses are with the same offset with 8 bytes boundary. memcmp() can align the src/dst

[PATCH v1 0/3] powerpc: memcmp() optimization

From: Simon Guo There is some room to optimize memcmp() in powerpc for following 2 cases: (1) Even src/dst addresses are not aligned with 8 bytes at the beginning, memcmp() can align them and go with .Llong comparision mode without fallback to .Lshort comparision mode do

[PATCH] selftests/powerpc: fix build error in powerpc ptrace selftests.

From: Simon Guo GCC 7 will take "r2" in clobber list as an error will it will get following build errors for powerpc ptrace selftests even with -fno-pic option: ptrace-tm-vsx.c: In function ‘tm_vsx’: ptrace-tm-vsx.c:42:2: error: PIC register clobbered by ‘r2’ in

[PATCH v16 15/15] selftests/powerpc: Fix a build issue

From: Anshuman Khandual Fixes the following build failure - cp_abort.c:90:3: error: ‘for’ loop initial declarations are only allowed in C99 or C11 mode for (int i = 0; i < NUM_LOOPS; i++) { ^ cp_abort.c:90:3: note: use option -std=c99, -std=gnu99, -std=c11 or

[PATCH v16 14/15] selftests/powerpc: Add .gitignore file for ptrace executables

From: Anshuman Khandual This patch adds a .gitignore file for all the executables in the ptrace test directory thus making invisible with git status query. Signed-off-by: Anshuman Khandual Signed-off-by: Simon Guo

[PATCH v16 13/15] selftests/powerpc: Add ptrace tests for TM SPR registers

From: Anshuman Khandual This patch adds ptrace interface test for TM SPR registers. This also adds ptrace interface based helper functions related to TM SPR registers access. Signed-off-by: Anshuman Khandual Signed-off-by: Simon Guo

[PATCH v16 12/15] selftests/powerpc: Add ptrace tests for VSX, VMX registers in suspended TM

From: Anshuman Khandual This patch adds ptrace interface test for VSX, VMX registers inside suspended TM context. Signed-off-by: Anshuman Khandual Signed-off-by: Simon Guo ---

[PATCH v16 11/15] selftests/powerpc: Add ptrace tests for VSX, VMX registers in TM

From: Anshuman Khandual This patch adds ptrace interface test for VSX, VMX registers inside TM context. This also adds ptrace interface based helper functions related to chckpointed VSX, VMX registers access. Signed-off-by: Anshuman Khandual

[PATCH v16 10/15] selftests/powerpc: Add ptrace tests for VSX, VMX registers

From: Anshuman Khandual This patch adds ptrace interface test for VSX, VMX registers. This also adds ptrace interface based helper functions related to VSX, VMX registers access. This also adds some assembly helper functions related to VSX and VMX registers.

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