On Fri, 2020-03-20 at 10:32:42 UTC, "Aneesh Kumar K.V" wrote:
> As per ISA and isync is only needed on instruction cache
> block invalidate. Remove the same from dcache invalidate.
>
> Signed-off-by: Aneesh Kumar K.V
Applied to powerpc next, thanks.
On Fri, Mar 20, 2020 at 08:38:42PM +0530, Aneesh Kumar K.V wrote:
> On 3/20/20 8:35 PM, Segher Boessenkool wrote:
> >On Fri, Mar 20, 2020 at 04:02:42PM +0530, Aneesh Kumar K.V wrote:
> >>As per ISA and isync is only needed on instruction cache
> >>block invalidate. Remove the same from dcache
On 3/20/20 8:35 PM, Segher Boessenkool wrote:
On Fri, Mar 20, 2020 at 04:02:42PM +0530, Aneesh Kumar K.V wrote:
As per ISA and isync is only needed on instruction cache
block invalidate. Remove the same from dcache invalidate.
Is that true on older CPUs?
That is what I found by checking
On Fri, Mar 20, 2020 at 04:02:42PM +0530, Aneesh Kumar K.V wrote:
> As per ISA and isync is only needed on instruction cache
> block invalidate. Remove the same from dcache invalidate.
Is that true on older CPUs?
Segher
As per ISA and isync is only needed on instruction cache
block invalidate. Remove the same from dcache invalidate.
Signed-off-by: Aneesh Kumar K.V
---
Note: IIUC we can also void the sync fore dcbf.
arch/powerpc/include/asm/cacheflush.h | 6 +-
1 file changed, 1 insertion(+), 5
