On Mon, Jun 4, 2018 at 12:44 PM, Haren Myneni wrote:
> On 06/03/2018 05:41 PM, Stewart Smith wrote:
>> Haren Myneni writes:
>>> On 06/01/2018 12:41 AM, Stewart Smith wrote:
Haren Myneni writes:
> NX increments readOffset by FIFO size in receive FIFO control register
> when CRB is re
On 06/03/2018 09:08 PM, Stewart Smith wrote:
> Haren Myneni writes:
>> On 06/03/2018 05:41 PM, Stewart Smith wrote:
>>> Haren Myneni writes:
On 06/01/2018 12:41 AM, Stewart Smith wrote:
> Haren Myneni writes:
>> NX increments readOffset by FIFO size in receive FIFO control register
Haren Myneni writes:
> On 06/03/2018 05:41 PM, Stewart Smith wrote:
>> Haren Myneni writes:
>>> On 06/01/2018 12:41 AM, Stewart Smith wrote:
Haren Myneni writes:
> NX increments readOffset by FIFO size in receive FIFO control register
> when CRB is read. But the index in RxFIFO has
On 06/03/2018 05:41 PM, Stewart Smith wrote:
> Haren Myneni writes:
>> On 06/01/2018 12:41 AM, Stewart Smith wrote:
>>> Haren Myneni writes:
NX increments readOffset by FIFO size in receive FIFO control register
when CRB is read. But the index in RxFIFO has to match with the
corres
Haren Myneni writes:
> On 06/01/2018 12:41 AM, Stewart Smith wrote:
>> Haren Myneni writes:
>>> NX increments readOffset by FIFO size in receive FIFO control register
>>> when CRB is read. But the index in RxFIFO has to match with the
>>> corresponding entry in FIFO maintained by VAS in kernel. O
On 06/01/2018 12:41 AM, Stewart Smith wrote:
> Haren Myneni writes:
>> NX increments readOffset by FIFO size in receive FIFO control register
>> when CRB is read. But the index in RxFIFO has to match with the
>> corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX
>> may be proces
Haren Myneni writes:
> NX increments readOffset by FIFO size in receive FIFO control register
> when CRB is read. But the index in RxFIFO has to match with the
> corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX
> may be processing incorrect CRBs and can cause CRB timeout.
>
>
On 05/31/2018 08:52 PM, Stewart Smith wrote:
> Haren Myneni writes:
>> NX increments readOffset by FIFO size in receive FIFO control register
>> when CRB is read. But the index in RxFIFO has to match with the
>> corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX
>> may be proces
Haren Myneni writes:
> NX increments readOffset by FIFO size in receive FIFO control register
> when CRB is read. But the index in RxFIFO has to match with the
> corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX
> may be processing incorrect CRBs and can cause CRB timeout.
>
>
NX increments readOffset by FIFO size in receive FIFO control register
when CRB is read. But the index in RxFIFO has to match with the
corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX
may be processing incorrect CRBs and can cause CRB timeout.
VAS FIFO offset is 0 when the r
NX increments readOffset by FIFO size in receive FIFO control register
when CRB is read. But the index in RxFIFO has to match with the
corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX
may be processing incorrect CRBs and can cause CRB timeout.
VAS FIFO offset is 0 when th
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