Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers

2018-06-03 Thread Oliver
On Mon, Jun 4, 2018 at 12:44 PM, Haren Myneni wrote: > On 06/03/2018 05:41 PM, Stewart Smith wrote: >> Haren Myneni writes: >>> On 06/01/2018 12:41 AM, Stewart Smith wrote: Haren Myneni writes: > NX increments readOffset by FIFO size in receive FIFO control register > when CRB is re

Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers

2018-06-03 Thread Haren Myneni
On 06/03/2018 09:08 PM, Stewart Smith wrote: > Haren Myneni writes: >> On 06/03/2018 05:41 PM, Stewart Smith wrote: >>> Haren Myneni writes: On 06/01/2018 12:41 AM, Stewart Smith wrote: > Haren Myneni writes: >> NX increments readOffset by FIFO size in receive FIFO control register

Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers

2018-06-03 Thread Stewart Smith
Haren Myneni writes: > On 06/03/2018 05:41 PM, Stewart Smith wrote: >> Haren Myneni writes: >>> On 06/01/2018 12:41 AM, Stewart Smith wrote: Haren Myneni writes: > NX increments readOffset by FIFO size in receive FIFO control register > when CRB is read. But the index in RxFIFO has

Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers

2018-06-03 Thread Haren Myneni
On 06/03/2018 05:41 PM, Stewart Smith wrote: > Haren Myneni writes: >> On 06/01/2018 12:41 AM, Stewart Smith wrote: >>> Haren Myneni writes: NX increments readOffset by FIFO size in receive FIFO control register when CRB is read. But the index in RxFIFO has to match with the corres

Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers

2018-06-03 Thread Stewart Smith
Haren Myneni writes: > On 06/01/2018 12:41 AM, Stewart Smith wrote: >> Haren Myneni writes: >>> NX increments readOffset by FIFO size in receive FIFO control register >>> when CRB is read. But the index in RxFIFO has to match with the >>> corresponding entry in FIFO maintained by VAS in kernel. O

Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers

2018-06-01 Thread Haren Myneni
On 06/01/2018 12:41 AM, Stewart Smith wrote: > Haren Myneni writes: >> NX increments readOffset by FIFO size in receive FIFO control register >> when CRB is read. But the index in RxFIFO has to match with the >> corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX >> may be proces

Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers

2018-06-01 Thread Stewart Smith
Haren Myneni writes: > NX increments readOffset by FIFO size in receive FIFO control register > when CRB is read. But the index in RxFIFO has to match with the > corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX > may be processing incorrect CRBs and can cause CRB timeout. > >

Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers

2018-05-31 Thread Haren Myneni
On 05/31/2018 08:52 PM, Stewart Smith wrote: > Haren Myneni writes: >> NX increments readOffset by FIFO size in receive FIFO control register >> when CRB is read. But the index in RxFIFO has to match with the >> corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX >> may be proces

Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers

2018-05-31 Thread Stewart Smith
Haren Myneni writes: > NX increments readOffset by FIFO size in receive FIFO control register > when CRB is read. But the index in RxFIFO has to match with the > corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX > may be processing incorrect CRBs and can cause CRB timeout. > >

[PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers

2018-05-31 Thread Haren Myneni
NX increments readOffset by FIFO size in receive FIFO control register when CRB is read. But the index in RxFIFO has to match with the corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX may be processing incorrect CRBs and can cause CRB timeout. VAS FIFO offset is 0 when the r

[PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers

2018-04-21 Thread Haren Myneni
NX increments readOffset by FIFO size in receive FIFO control register when CRB is read. But the index in RxFIFO has to match with the corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX may be processing incorrect CRBs and can cause CRB timeout. VAS FIFO offset is 0 when th