On Thu, 2007-08-02 at 15:56 +1000, Michael Neuling wrote:
But even in the case of a checkpoint restart, the ordering will be
preserved as the NIA we get as part of the checkpoint will have all
previous instructions complete and none of the following instructions
started.
Instruction
But even in the case of a checkpoint restart, the ordering will be
preserved as the NIA we get as part of the checkpoint will have all
previous instructions complete and none of the following instructions
started.
Instruction completion isn't enough to ensure storage ordering. The
On Thu, 2007-08-02 at 18:56 +1000, Michael Neuling wrote:
But even in the case of a checkpoint restart, the ordering will be
preserved as the NIA we get as part of the checkpoint will have
all
previous instructions complete and none of the following
instructions
started.
On Thu, 2007-08-02 at 19:03 +1000, Michael Neuling wrote:
Ok, that was missing from your description :-)
Sorry... so ditch the barriers?
As you like. The reason why you can ditch them is purely because you
know for sure that the only case the firmware will access those shadows
from
We sometimes change the vmalloc segment in slb_flush_and_rebolt but we
never updated with slb shadow buffer. This fixes it. Thanks to paulus
for finding this.
Also added some write barriers to ensure the shadow buffer is always
valid.
Signed-off-by: Michael Neuling [EMAIL PROTECTED]
---
On Fri, 2007-08-03 at 11:55 +1000, Michael Neuling wrote:
We sometimes change the vmalloc segment in slb_flush_and_rebolt but we
never updated with slb shadow buffer. This fixes it. Thanks to paulus
for finding this.
Also added some write barriers to ensure the shadow buffer is always
On Wed, 2007-08-01 at 16:02 +1000, Michael Neuling wrote:
--- linux-2.6-ozlabs.orig/arch/powerpc/kernel/entry_64.S
+++ linux-2.6-ozlabs/arch/powerpc/kernel/entry_64.S
@@ -389,7 +389,9 @@ BEGIN_FTR_SECTION
ld r9,PACA_SLBSHADOWPTR(r13)
li r12,0
std
On Wed, 2007-08-01 at 16:02 +1000, Michael Neuling wrote:
We sometimes change the vmalloc segment in slb_flush_and_rebolt but we
never updated with slb shadow buffer. This fixes it. Thanks to paulus
for finding this.
Also added some write barriers to ensure the shadow buffer is always
On Wed, 2007-08-01 at 16:02 +1000, Michael Neuling wrote:
We sometimes change the vmalloc segment in slb_flush_and_rebolt but we
never updated with slb shadow buffer. This fixes it. Thanks to paulus
for finding this.
Also added some write barriers to ensure the shadow buffer is
On Thu, 2007-08-02 at 09:32 +1000, Michael Neuling wrote:
On Wed, 2007-08-01 at 16:02 +1000, Michael Neuling wrote:
We sometimes change the vmalloc segment in slb_flush_and_rebolt but we
never updated with slb shadow buffer. This fixes it. Thanks to paulus
for finding this.
The first block of code detects the need for a demotion and changes the
global mmu_vmalloc_psize, along with changing the value on the local CPU
(and flushing it's SLB). But other CPUs still have the old values.
The second block of code checks if the global value matches the per-CPU
value
--- linux-2.6-ozlabs.orig/arch/powerpc/kernel/entry_64.S
+++ linux-2.6-ozlabs/arch/powerpc/kernel/entry_64.S
@@ -389,7 +389,9 @@ BEGIN_FTR_SECTION
ld r9,PACA_SLBSHADOWPTR(r13)
li r12,0
std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
+ eieio
std
We sometimes change the vmalloc segment in slb_flush_and_rebolt but we
never updated with slb shadow buffer. This fixes it. Thanks to paulus
for finding this.
Also added some write barriers to ensure the shadow buffer is always
valid.
Signed-off-by: Michael Neuling [EMAIL PROTECTED]
---
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