On Nov 23, 2008, at 11:01 PM, Kumar Gala wrote:
On Nov 22, 2008, at 10:01 PM, Trent Piepho wrote:
On Sat, 22 Nov 2008, Milton Miller wrote:
On Thu Nov 20 at 06:14:30 EST in 2008, Trent Piepho wrote:
- li r7,0
- lis r6,PAGE_OFFSET at h
- ori r6,r6,PAGE_OFFSET at
On Nov 22, 2008, at 10:01 PM, Trent Piepho wrote:
On Sat, 22 Nov 2008, Milton Miller wrote:
On Thu Nov 20 at 06:14:30 EST in 2008, Trent Piepho wrote:
- li r7,0
- lis r6,PAGE_OFFSET at h
- ori r6,r6,PAGE_OFFSET at l
- rlwimi r6,r7,0,20,31
+ lis
The initial TLB mapping for the kernel boot didn't set the memory coherent
attribute, MAS2[M], in SMP mode.
If this code supported booting a secondary processor, which it doesn't yet,
but suppose it did, then when a secondary processor boots, it would have
probably signaled the primary processor
On Nov 19, 2008, at 1:14 PM, Trent Piepho wrote:
The initial TLB mapping for the kernel boot didn't set the memory
coherent
attribute, MAS2[M], in SMP mode.
If this code supported booting a secondary processor, which it
doesn't yet,
but suppose it did, then when a secondary processor
