From: Wang Qing <wangq...@vivo.com>
We don't know anything about the cache topology info without ACPI,
but in fact we can get it from DT like:
* cpu0: cpu@000 {
* next-level-cache = <&L2_1>;
* L2_1: l2-cache {
* compatible = "cache";
* next-level-cache = <&L3_1>;
* };
* L3_1: l3-cache {
* compatible = "cache";
* };
* };
*
* cpu1: cpu@001 {
* next-level-cache = <&L2_1>;
* cpu-idle-states = <&clusteroff_l &mcusysoff
* &system_mem &system_pll
&system_bus
* &s2idle>;
* };
* cpu2: cpu@002 {
* L2_2: l2-cache {
* compatible = "cache";
* next-level-cache = <&L3_1>;
* };
* };
*
* cpu3: cpu@003 {
* next-level-cache = <&L2_2>;
* };
Building the cache topology has many benefits, here is a part of useage.
Wang Qing (3):
sched: topology: add input parameter for sched_domain_flags_f()
arch_topology: support for describing cache topology from DT
arm64: add arm64 default topology
arch/arm64/kernel/smp.c | 56 ++++++++++++++++++++++++++
arch/powerpc/kernel/smp.c | 4 +-
arch/x86/kernel/smpboot.c | 8 ++--
drivers/base/arch_topology.c | 89 +++++++++++++++++++++++++++++++++++++++++-
include/linux/arch_topology.h | 4 ++
include/linux/sched/topology.h | 10 ++---
kernel/sched/topology.c | 2 +-
7 files changed, 160 insertions(+), 13 deletions(-)
--
2.7.4
