[PATCH 02/11] powerpc/8xx: remove tests on PGDIR entry validity

2015-04-19 Thread Christophe Leroy
Kernel MMU handling code handles validity of entries via _PMD_PRESENT which corresponds to V bit in MD_TWC and MI_TWC. When the V bit is not set, MPC8xx triggers TLBError exception. So we don't have to check that and branch ourself to TLBError. We can set TLB entries with non present entries,

Re: [PATCH 02/11] powerpc/8xx: remove tests on PGDIR entry validity

2015-01-05 Thread Joakim Tjernlund
On Tue, 2014-12-16 at 16:03 +0100, Christophe Leroy wrote: Kernel MMU handling code handles validity of entries via _PMD_PRESENT which corresponds to V bit in MD_TWC and MI_TWC. When the V bit is not set, MPC8xx triggers TLBError exception. So we don't have to check that and branch ourself to

[PATCH 02/11] powerpc/8xx: remove tests on PGDIR entry validity

2014-12-16 Thread Christophe Leroy
Kernel MMU handling code handles validity of entries via _PMD_PRESENT which corresponds to V bit in MD_TWC and MI_TWC. When the V bit is not set, MPC8xx triggers TLBError exception. So we don't have to check that and branch ourself to TLBError. We can set TLB entries with non present entries,