...@freescale.com
Date: 09/12/2009 09:56
Subject: Re: [PATCH 04/10] 8xx: Always pin kernel instruction TLB
On Wed, 2009-12-09 at 08:39 +0100, Joakim Tjernlund wrote:
The later isn't as simple :) I believe the bulk of such code in
entry_32.S.
Yeah but it would be useful for hash I suppose if one really
On Wed, 2009-12-09 at 08:39 +0100, Joakim Tjernlund wrote:
The later isn't as simple :) I believe the bulk of such code in
entry_32.S.
Yeah but it would be useful for hash I suppose if one really wants to
boot with nobats. Though at least on hash most of the time we have ways
to recover by mean
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 09/12/2009 09:56:35:
On Wed, 2009-12-09 at 08:39 +0100, Joakim Tjernlund wrote:
The later isn't as simple :) I believe the bulk of such code in
entry_32.S.
Yeah but it would be useful for hash I suppose if one really wants to
boot
On Fri, 2009-11-20 at 11:21 +0100, Joakim Tjernlund wrote:
Various kernel asm modifies SRR0/SRR1 just before executing
a rfi. If such code crosses a page boundary you risk a TLB miss
which will clobber SRR0/SRR1. Avoid this by always pinning
kernel instruction TLB space.
Signed-off-by:
...@mrv.com
Date: 09/12/2009 05:20
Subject: Re: [PATCH 04/10] 8xx: Always pin kernel instruction TLB
On Fri, 2009-11-20 at 11:21 +0100, Joakim Tjernlund wrote:
Various kernel asm modifies SRR0/SRR1 just before executing
a rfi. If such code crosses a page boundary you risk a TLB miss
which
Various kernel asm modifies SRR0/SRR1 just before executing
a rfi. If such code crosses a page boundary you risk a TLB miss
which will clobber SRR0/SRR1. Avoid this by always pinning
kernel instruction TLB space.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
Dan Malek d...@embeddedalley.com wrote on 14/11/2009 19:08:43:
On Nov 14, 2009, at 2:42 AM, Joakim Tjernlund wrote:
. Avoid this by always pinning
kernel instruction TLB space.
You may as well map the data space, too, since you have
reserved the entries. Take advantage of
Various kernel asm modifies SRR0/SRR1 just before executing
a rfi. If such code crosses a page boundary you risk a TLB miss
which will clobber SRR0/SRR1. Avoid this by always pinning
kernel instruction TLB space.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
Various kernel asm modifies SRR0/SRR1 just before executing
a rfi. If such code crosses a page boundary you risk a TLB miss
which will clobber SRR0/SRR1. Avoid this by always pinning
kernel instruction TLB space.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
On Nov 14, 2009, at 2:42 AM, Joakim Tjernlund wrote:
. Avoid this by always pinning
kernel instruction TLB space.
You may as well map the data space, too, since you have
reserved the entries. Take advantage of that performance.
Also, some processor variants have very few TLB entries,
Dan Malek d...@embeddedalley.com wrote on 14/11/2009 19:08:43:
On Nov 14, 2009, at 2:42 AM, Joakim Tjernlund wrote:
. Avoid this by always pinning
kernel instruction TLB space.
You may as well map the data space, too, since you have
reserved the entries. Take advantage of that
On Sat, 2009-11-14 at 20:08 +0100, Joakim Tjernlund wrote:
Dan Malek d...@embeddedalley.com wrote on 14/11/2009 19:08:43:
On Nov 14, 2009, at 2:42 AM, Joakim Tjernlund wrote:
. Avoid this by always pinning
kernel instruction TLB space.
You may as well map the data space, too,
How to make better use of the remaining ITLB slots is tricky.
Somehow one would want to map at lest one to modules but I cannot see how.
No. If you use modules, you pay the price. Sane embedded solutions
running in tight environments don't use modules :-) No point pinning
TLB
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