Re: [PATCH 1/3] powerpc/pseries/cpuhp: cache node corrections

2021-09-20 Thread Daniel Henrique Barboza
On 9/20/21 10:55, Nathan Lynch wrote: On pseries, cache nodes in the device tree can be added and removed by the CPU DLPAR code as well as the partition migration (mobility) code. PowerVM partitions in dedicated processor mode typically have L2 and L3 cache nodes. The CPU DLPAR code has the

[PATCH 1/3] powerpc/pseries/cpuhp: cache node corrections

2021-09-20 Thread Nathan Lynch
On pseries, cache nodes in the device tree can be added and removed by the CPU DLPAR code as well as the partition migration (mobility) code. PowerVM partitions in dedicated processor mode typically have L2 and L3 cache nodes. The CPU DLPAR code has the following shortcomings: * Cache nodes