From: chenhui zhao chenhui.z...@freescale.com
Issue:
As a master, the PCI IP block can combine a memory write to the last PCI double
word (4 bytes) of a cacheline with a 4 byte memory write to the first PCI double
word of the subsequent cacheline. This affects 32-bit PCI target devices that
On Mar 6, 2012, at 3:10 AM, Zhao Chenhui wrote:
+ if ((fsl_svr_is(SVR_8548) || fsl_svr_is(SVR_8548_E))
Should this also have 8547, 8547E, 8545, 8545E, 8543, 8543E?
Yes. I will include these chips.
-Chenhui
+ !early_find_capability(hose, 0, 0,
From: chenhui zhao chenhui.z...@freescale.com
Issue:
As a master, the PCI IP block can combine a memory write to the last PCI double
word (4 bytes) of a cacheline with a 4 byte memory write to the first PCI double
word of the subsequent cacheline. This affects 32-bit PCI target devices that
On Mar 6, 2012, at 3:10 AM, Zhao Chenhui wrote:
+ if ((fsl_svr_is(SVR_8548) || fsl_svr_is(SVR_8548_E))
Should this also have 8547, 8547E, 8545, 8545E, 8543, 8543E?
+ !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) {
+
