Bounine, Alexandre wrote:
capable to receive and keep only one PW message. Therefore, I copy it
into the driver's FIFO and re-enable HW Rx queue (it is called queue but
can accept only one entry) ASAP. I have a test setup that is capable
generate multiple PW messages and see many messages
Micha Nelissen wrote:
Primarily due to the single entry queue, the order of checking is
probably insignificant? :-)
Help sometimes only but gives a feeling that I did all that is possible
;)
Anyway, I don't mind changing the order.
Micha
___
Alexandre Bounine wrote:
- Rearranged RIO port-write interrupt handling to perform message buffering
as soon as possible.
I don't understand this comment: you still schedule work to read the
port-write queue; so how is this message buffering performed as soon as
possible?
- Modified to
Micha Nelissen wrote:
Alexandre Bounine wrote:
- Rearranged RIO port-write interrupt handling to perform message
buffering
as soon as possible.
I don't understand this comment: you still schedule work to read the
port-write queue; so how is this message buffering performed as soon
as
- Rearranged RIO port-write interrupt handling to perform message buffering
as soon as possible.
- Modified to disable port-write controller when clearing Transaction Error (TE)
bit.
Signed-off-by: Alexandre Bounine alexandre.boun...@idt.com
Reviewed-by: Thomas Moll thomas.m...@sysgo.com
Cc: Matt
