On Tue, Dec 20, 2011 at 12:47 AM, Scott Wood scottw...@freescale.com wrote:
On 12/19/2011 05:05 AM, Li Yang wrote:
On Sat, Dec 17, 2011 at 1:59 AM, Scott Wood scottw...@freescale.com wrote:
On 12/15/2011 08:44 PM, LiuShuo wrote:
hi Artem,
Could this patch be applied now and we make a
On 12/20/2011 03:08 AM, Li Yang wrote:
On Tue, Dec 20, 2011 at 12:47 AM, Scott Wood scottw...@freescale.com wrote:
On 12/19/2011 05:05 AM, Li Yang wrote:
On Sat, Dec 17, 2011 at 1:59 AM, Scott Wood scottw...@freescale.com wrote:
On 12/15/2011 08:44 PM, LiuShuo wrote:
hi Artem,
Could this
On Sat, Dec 17, 2011 at 1:59 AM, Scott Wood scottw...@freescale.com wrote:
On 12/15/2011 08:44 PM, LiuShuo wrote:
hi Artem,
Could this patch be applied now and we make a independent patch for bad
block information
migration later?
This patch is not safe to use without migration.
Hi Scott,
On 12/19/2011 05:05 AM, Li Yang wrote:
On Sat, Dec 17, 2011 at 1:59 AM, Scott Wood scottw...@freescale.com wrote:
On 12/15/2011 08:44 PM, LiuShuo wrote:
hi Artem,
Could this patch be applied now and we make a independent patch for bad
block information
migration later?
This patch is not
On 12/17/2011 08:35 AM, Artem Bityutskiy wrote:
On Mon, 2011-12-12 at 15:30 -0600, Scott Wood wrote:
On 12/12/2011 03:19 PM, Artem Bityutskiy wrote:
On Mon, 2011-12-12 at 15:15 -0600, Scott Wood wrote:
NAND chips come from the factory with bad blocks marked at a certain
offset into each page.
On 12/19/2011 12:38 PM, Scott Wood wrote:
On 12/17/2011 08:35 AM, Artem Bityutskiy wrote:
It looks like currently you can re-define chip-read_page, so I guess
you should rework MTD and make chip-write_page re-definable?
Unless something has changed very recently, there is no chip-read_page
On Mon, 2011-12-12 at 15:30 -0600, Scott Wood wrote:
On 12/12/2011 03:19 PM, Artem Bityutskiy wrote:
On Mon, 2011-12-12 at 15:15 -0600, Scott Wood wrote:
NAND chips come from the factory with bad blocks marked at a certain
offset into each page. This offset is normally in the OOB area, but
On 12/15/2011 08:44 PM, LiuShuo wrote:
hi Artem,
Could this patch be applied now and we make a independent patch for bad
block information
migration later?
This patch is not safe to use without migration.
-Scott
___
Linuxppc-dev mailing list
On 12/14/2011 10:59 PM, Li Yang wrote:
The limitation of the proposed bad block marker migration is that you
need to make sure the migration is done and only done once. If it is
done more than once, the factory bad block marker is totally messed
up. It requires a complex mechanism to
于 2011年12月15日 04:15, Scott Wood 写道:
On 12/14/2011 02:41 AM, LiuShuo wrote:
于 2011年12月13日 10:46, LiuShuo 写道:
于 2011年12月13日 05:30, Scott Wood 写道:
On 12/12/2011 03:19 PM, Artem Bityutskiy wrote:
On Mon, 2011-12-12 at 15:15 -0600, Scott Wood wrote:
NAND chips come from the factory with bad
于 2011年12月13日 10:46, LiuShuo 写道:
于 2011年12月13日 05:30, Scott Wood 写道:
On 12/12/2011 03:19 PM, Artem Bityutskiy wrote:
On Mon, 2011-12-12 at 15:15 -0600, Scott Wood wrote:
NAND chips come from the factory with bad blocks marked at a certain
offset into each page. This offset is normally in the
On 12/14/2011 02:41 AM, LiuShuo wrote:
于 2011年12月13日 10:46, LiuShuo 写道:
于 2011年12月13日 05:30, Scott Wood 写道:
On 12/12/2011 03:19 PM, Artem Bityutskiy wrote:
On Mon, 2011-12-12 at 15:15 -0600, Scott Wood wrote:
NAND chips come from the factory with bad blocks marked at a certain
offset into
On 12/13/2011 09:41 PM, LiuShuo wrote:
于 2011年12月13日 05:09, Artem Bityutskiy 写道:
On Tue, 2011-12-06 at 18:09 -0600, Scott Wood wrote:
On 12/03/2011 10:31 PM, shuo@freescale.com wrote:
From: Liu Shuoshuo@freescale.com
Freescale FCM controller has a 2K size limitation of buffer RAM. In
On Thu, Dec 15, 2011 at 4:15 AM, Scott Wood scottw...@freescale.com wrote:
On 12/14/2011 02:41 AM, LiuShuo wrote:
于 2011年12月13日 10:46, LiuShuo 写道:
于 2011年12月13日 05:30, Scott Wood 写道:
On 12/12/2011 03:19 PM, Artem Bityutskiy wrote:
On Mon, 2011-12-12 at 15:15 -0600, Scott Wood wrote:
NAND
于 2011年12月13日 05:09, Artem Bityutskiy 写道:
On Tue, 2011-12-06 at 18:09 -0600, Scott Wood wrote:
On 12/03/2011 10:31 PM, shuo@freescale.com wrote:
From: Liu Shuoshuo@freescale.com
Freescale FCM controller has a 2K size limitation of buffer RAM. In order
to support the Nand flash chip
On Tue, 2011-12-06 at 18:09 -0600, Scott Wood wrote:
On 12/03/2011 10:31 PM, shuo@freescale.com wrote:
From: Liu Shuo shuo@freescale.com
Freescale FCM controller has a 2K size limitation of buffer RAM. In order
to support the Nand flash chip whose page size is larger than 2K
On 12/12/2011 03:09 PM, Artem Bityutskiy wrote:
On Tue, 2011-12-06 at 18:09 -0600, Scott Wood wrote:
On 12/03/2011 10:31 PM, shuo@freescale.com wrote:
From: Liu Shuo shuo@freescale.com
Freescale FCM controller has a 2K size limitation of buffer RAM. In order
to support the Nand flash
On Mon, 2011-12-12 at 15:15 -0600, Scott Wood wrote:
NAND chips come from the factory with bad blocks marked at a certain
offset into each page. This offset is normally in the OOB area, but
since we change the layout from 4k data, 128 byte oob to 2k data, 64
byte oob, 2k data, 64 byte oob the
On 12/12/2011 03:19 PM, Artem Bityutskiy wrote:
On Mon, 2011-12-12 at 15:15 -0600, Scott Wood wrote:
NAND chips come from the factory with bad blocks marked at a certain
offset into each page. This offset is normally in the OOB area, but
since we change the layout from 4k data, 128 byte oob
于 2011年12月13日 05:30, Scott Wood 写道:
On 12/12/2011 03:19 PM, Artem Bityutskiy wrote:
On Mon, 2011-12-12 at 15:15 -0600, Scott Wood wrote:
NAND chips come from the factory with bad blocks marked at a certain
offset into each page. This offset is normally in the OOB area, but
since we change the
于 2011年12月08日 03:11, Scott Wood 写道:
On 12/06/2011 09:55 PM, LiuShuo wrote:
于 2011年12月07日 08:09, Scott Wood 写道:
On 12/03/2011 10:31 PM, shuo@freescale.com wrote:
From: Liu Shuoshuo@freescale.com
Freescale FCM controller has a 2K size limitation of buffer RAM. In
order
to support the
On 12/08/2011 04:44 AM, LiuShuo wrote:
于 2011年12月08日 03:11, Scott Wood 写道:
And if we do want to make such assumptions, we could rip out all usage
of index/column here, and just handle oob and full page cases.
The function nand_do_write_ops() in nandbase.c is a Nand internal
interface.
It
On 12/06/2011 09:55 PM, LiuShuo wrote:
于 2011年12月07日 08:09, Scott Wood 写道:
On 12/03/2011 10:31 PM, shuo@freescale.com wrote:
From: Liu Shuoshuo@freescale.com
Freescale FCM controller has a 2K size limitation of buffer RAM. In
order
to support the Nand flash chip whose page size is
On Sun, 2011-12-04 at 12:31 +0800, shuo@freescale.com wrote:
From: Liu Shuo shuo@freescale.com
Freescale FCM controller has a 2K size limitation of buffer RAM. In order
to support the Nand flash chip whose page size is larger than 2K bytes,
we read/write 2k data repeatedly by issuing
On Mon, 2011-12-05 at 13:46 -0600, Scott Wood wrote:
Because this is a controller resource, shared by multiple NAND chips
that may be different page sizes (even if not, it's adding another point
of synchronization required between initialization of different chips).
I don't think it's worth
On 12/03/2011 10:31 PM, shuo@freescale.com wrote:
From: Liu Shuo shuo@freescale.com
Freescale FCM controller has a 2K size limitation of buffer RAM. In order
to support the Nand flash chip whose page size is larger than 2K bytes,
we read/write 2k data repeatedly by issuing
于 2011年12月07日 08:09, Scott Wood 写道:
On 12/03/2011 10:31 PM, shuo@freescale.com wrote:
From: Liu Shuoshuo@freescale.com
Freescale FCM controller has a 2K size limitation of buffer RAM. In order
to support the Nand flash chip whose page size is larger than 2K bytes,
we read/write 2k data
On 12/05/2011 12:47 AM, Artem Bityutskiy wrote:
On Sun, 2011-12-04 at 12:31 +0800, shuo@freescale.com wrote:
+/*
+ * Freescale FCM controller has a 2K size limitation of buffer
+ * RAM, so elbc_fcm_ctrl-buffer have to be used if writesize
+
From: Liu Shuo shuo@freescale.com
Freescale FCM controller has a 2K size limitation of buffer RAM. In order
to support the Nand flash chip whose page size is larger than 2K bytes,
we read/write 2k data repeatedly by issuing FIR_OP_RB/FIR_OP_WB and save
them to a large buffer.
Signed-off-by:
On Sun, 2011-12-04 at 12:31 +0800, shuo@freescale.com wrote:
+ /*
+ * Freescale FCM controller has a 2K size limitation of buffer
+ * RAM, so elbc_fcm_ctrl-buffer have to be used if writesize
+ * of chip is greater than 2048.
+
On 11/24/2011 01:37 AM, Li Yang-R58472 wrote:
+static void io_to_buffer(struct mtd_info *mtd, int subpage, int oob)
+{
+struct nand_chip *chip = mtd-priv;
+struct fsl_elbc_mtd *priv = chip-priv;
+struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv-ctrl-nand;
+void *src, *dst;
+
On 11/23/2011 06:41 PM, b35...@freescale.com wrote:
From: Liu Shuo b35...@freescale.com
Freescale FCM controller has a 2K size limitation of buffer RAM. In order
to support the Nand flash chip whose page size is larger than 2K bytes,
we read/write 2k data repeatedly by issuing
On 11/28/2011 03:48 PM, Scott Wood wrote:
On 11/23/2011 06:41 PM, b35...@freescale.com wrote:
From: Liu Shuo b35...@freescale.com
Freescale FCM controller has a 2K size limitation of buffer RAM. In order
to support the Nand flash chip whose page size is larger than 2K bytes,
we read/write 2k
On Thu, 2011-11-24 at 07:49 +, Li Yang-R58472 wrote:
Subject: Re: [PATCH 3/3] mtd/nand : workaround for Freescale FCM to support
large-page Nand chip
On Thu, 2011-11-24 at 08:41 +0800, b35...@freescale.com wrote:
+ /*
+* Freescale FCM controller has
于 2011年11月24日 16:16, Artem Bityutskiy 写道:
On Thu, 2011-11-24 at 07:49 +, Li Yang-R58472 wrote:
Subject: Re: [PATCH 3/3] mtd/nand : workaround for Freescale FCM to support
large-page Nand chip
On Thu, 2011-11-24 at 08:41 +0800, b35...@freescale.com wrote
On Thu, 2011-11-24 at 18:02 +0800, LiuShuo wrote:
于 2011年11月24日 16:16, Artem Bityutskiy 写道:
On Thu, 2011-11-24 at 07:49 +, Li Yang-R58472 wrote:
Subject: Re: [PATCH 3/3] mtd/nand : workaround for Freescale FCM to
support
large-page Nand chip
On Thu, 2011-11-24 at 08:41 +0800, b35
From: Liu Shuo b35...@freescale.com
Freescale FCM controller has a 2K size limitation of buffer RAM. In order
to support the Nand flash chip whose page size is larger than 2K bytes,
we read/write 2k data repeatedly by issuing FIR_OP_RB/FIR_OP_WB and save
them to a large buffer.
Signed-off-by:
Subject: [PATCH 3/3] mtd/nand : workaround for Freescale FCM to support
large-page Nand chip
From: Liu Shuo b35...@freescale.com
Freescale FCM controller has a 2K size limitation of buffer RAM. In order
to support the Nand flash chip whose page size is larger than 2K bytes,
we read/write
On Thu, 2011-11-24 at 08:41 +0800, b35...@freescale.com wrote:
+ /*
+* Freescale FCM controller has a 2K size limitation of buffer
+* RAM, so elbc_fcm_ctrl-buffer have to be used if writesize
+* of chip is greater than 2048.
+
Subject: Re: [PATCH 3/3] mtd/nand : workaround for Freescale FCM to support
large-page Nand chip
On Thu, 2011-11-24 at 08:41 +0800, b35...@freescale.com wrote:
+ /*
+* Freescale FCM controller has a 2K size limitation of
buffer
+* RAM, so
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