Re: [PATCH 3/3] powerpc/64s/idle: POWER9 ESL=0 stop avoid save/restore overhead

2018-03-31 Thread Michael Ellerman
Nicholas Piggin writes: > When stop is executed with EC=ESL=0, it appears to execute like a > normal instruction (resuming from NIP when woken by interrupt). So all > the save/restore handling can be avoided completely. In particular NV > GPRs do not have to be saved, and MSR

Re: [PATCH 3/3] powerpc/64s/idle: POWER9 ESL=0 stop avoid save/restore overhead

2018-03-05 Thread Nicholas Piggin
On Mon, 5 Mar 2018 10:01:01 +1100 Paul Mackerras wrote: > On Thu, Mar 01, 2018 at 09:57:34PM +1000, Nicholas Piggin wrote: > > On Thu, 1 Mar 2018 00:04:39 +0530 > > Vaidyanathan Srinivasan wrote: > > > > > * Nicholas Piggin

Re: [PATCH 3/3] powerpc/64s/idle: POWER9 ESL=0 stop avoid save/restore overhead

2018-03-04 Thread Paul Mackerras
On Thu, Mar 01, 2018 at 09:57:34PM +1000, Nicholas Piggin wrote: > On Thu, 1 Mar 2018 00:04:39 +0530 > Vaidyanathan Srinivasan wrote: > > > * Nicholas Piggin [2017-11-18 00:08:07]: [snip] > > > diff --git a/arch/powerpc/platforms/powernv/idle.c > >

Re: [PATCH 3/3] powerpc/64s/idle: POWER9 ESL=0 stop avoid save/restore overhead

2018-03-01 Thread Nicholas Piggin
On Thu, 1 Mar 2018 00:04:39 +0530 Vaidyanathan Srinivasan wrote: > * Nicholas Piggin [2017-11-18 00:08:07]: > > > When stop is executed with EC=ESL=0, it appears to execute like a > > normal instruction (resuming from NIP when woken by interrupt).

Re: [PATCH 3/3] powerpc/64s/idle: POWER9 ESL=0 stop avoid save/restore overhead

2018-02-28 Thread Vaidyanathan Srinivasan
* Nicholas Piggin [2017-11-18 00:08:07]: > When stop is executed with EC=ESL=0, it appears to execute like a > normal instruction (resuming from NIP when woken by interrupt). So all > the save/restore handling can be avoided completely. In particular NV > GPRs do not have to

[PATCH 3/3] powerpc/64s/idle: POWER9 ESL=0 stop avoid save/restore overhead

2017-11-17 Thread Nicholas Piggin
When stop is executed with EC=ESL=0, it appears to execute like a normal instruction (resuming from NIP when woken by interrupt). So all the save/restore handling can be avoided completely. In particular NV GPRs do not have to be saved, and MSR does not have to be switched back to kernel MSR. So