powerpc flush_inval_dcache_range() was buggy until v5.3-rc1 (was Re: [PATCH 4/4] powerpc/64: reuse PPC32 static inline flush_dcache_range())

2019-08-08 Thread Michael Ellerman
[ deliberately broke threading so this doesn't get buried ] Christophe Leroy writes: > diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S > index a4fd536efb44..1b0a42c50ef1 100644 > --- a/arch/powerpc/kernel/misc_64.S > +++ b/arch/powerpc/kernel/misc_64.S > @@ -115,35

Re: [PATCH 4/4] powerpc/64: reuse PPC32 static inline flush_dcache_range()

2019-07-09 Thread Segher Boessenkool
On Tue, Jul 09, 2019 at 08:21:54AM +0530, Aneesh Kumar K.V wrote: > On 7/9/19 7:50 AM, Oliver O'Halloran wrote: > >I don't think it's that, there's some magic in flush_icache_range() to > >handle dropping prefetched instructions on 970. > > > >>So overall wondering why we need that extra barriers

Re: [PATCH 4/4] powerpc/64: reuse PPC32 static inline flush_dcache_range()

2019-07-08 Thread Oliver O'Halloran
On Tue, Jul 9, 2019 at 12:52 PM Aneesh Kumar K.V wrote: > > On 7/9/19 7:50 AM, Oliver O'Halloran wrote: > > On Tue, Jul 9, 2019 at 12:22 AM Aneesh Kumar K.V > > wrote: > >> > >> Christophe Leroy writes: > >> > >>> *snip* > >>> + if (IS_ENABLED(CONFIG_PPC64)) > >>> + isync(); >

Re: [PATCH 4/4] powerpc/64: reuse PPC32 static inline flush_dcache_range()

2019-07-08 Thread Aneesh Kumar K.V
On 7/9/19 7:50 AM, Oliver O'Halloran wrote: On Tue, Jul 9, 2019 at 12:22 AM Aneesh Kumar K.V wrote: Christophe Leroy writes: *snip* + if (IS_ENABLED(CONFIG_PPC64)) + isync(); } Was checking with Michael about why we need that extra isync. Michael pointed this came via

Re: [PATCH 4/4] powerpc/64: reuse PPC32 static inline flush_dcache_range()

2019-07-08 Thread Oliver O'Halloran
On Tue, Jul 9, 2019 at 12:22 AM Aneesh Kumar K.V wrote: > > Christophe Leroy writes: > > > *snip* > > + if (IS_ENABLED(CONFIG_PPC64)) > > + isync(); > > } > > > Was checking with Michael about why we need that extra isync. Michael > pointed this came via > >

Re: [PATCH 4/4] powerpc/64: reuse PPC32 static inline flush_dcache_range()

2019-07-08 Thread Aneesh Kumar K.V
Christophe Leroy writes: > This patch drops the assembly PPC64 version of flush_dcache_range() > and re-uses the PPC32 static inline version. > > With GCC 8.1, the following code is generated: > > void flush_test(unsigned long start, unsigned long stop) > { > flush_dcache_range(start,

Re: [PATCH 4/4] powerpc/64: reuse PPC32 static inline flush_dcache_range()

2019-07-07 Thread Michael Ellerman
On Tue, 2019-05-14 at 09:05:16 UTC, Christophe Leroy wrote: > This patch drops the assembly PPC64 version of flush_dcache_range() > and re-uses the PPC32 static inline version. > > With GCC 8.1, the following code is generated: > > void flush_test(unsigned long start, unsigned long stop) > { >

[PATCH 4/4] powerpc/64: reuse PPC32 static inline flush_dcache_range()

2019-05-14 Thread Christophe Leroy
This patch drops the assembly PPC64 version of flush_dcache_range() and re-uses the PPC32 static inline version. With GCC 8.1, the following code is generated: void flush_test(unsigned long start, unsigned long stop) { flush_dcache_range(start, stop); } 0130 <.flush_test>: