On Thu, Jul 13, 2017 at 5:47 PM, Segher Boessenkool
wrote:
> On Thu, Jul 13, 2017 at 01:25:48PM +1000, Matt Brown wrote:
>> + case 585: /* isel */
>
> The secondary opcode for isel is only 5 bits, not 10 like most other
> insns have.
Yet another
On Thu, Jul 13, 2017 at 01:25:48PM +1000, Matt Brown wrote:
> + case 585: /* isel */
The secondary opcode for isel is only 5 bits, not 10 like most other
insns have.
> + mb = (instr >> 6) & 0x1f; /* bc */
> + val = (regs->ccr >> (mb +
This add emulation for the isel instruction.
Signed-off-by: Matt Brown
---
arch/powerpc/lib/sstep.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 3228783..bb0e301 100644
---