On Mar 20, 2009, at 12:48 AM, Benjamin Herrenschmidt wrote:
On Wed, 2009-03-11 at 10:18 -0500, Kumar Gala wrote:
CoreInt provides a mechansim to deliver the IRQ vector directly
into the core on an interrupt (via the SPR EPR) rather than having
to go IACK on the PIC. This is suppose to
On Fri, 2009-03-20 at 06:47 -0500, Kumar Gala wrote:
On Mar 20, 2009, at 12:48 AM, Benjamin Herrenschmidt wrote:
On Wed, 2009-03-11 at 10:18 -0500, Kumar Gala wrote:
CoreInt provides a mechansim to deliver the IRQ vector directly
into the core on an interrupt (via the SPR EPR) rather than
On Wed, 2009-03-11 at 10:18 -0500, Kumar Gala wrote:
CoreInt provides a mechansim to deliver the IRQ vector directly
into the core on an interrupt (via the SPR EPR) rather than having
to go IACK on the PIC. This is suppose to provide an improvment
in interrupt latency by reducing the time to
CoreInt provides a mechansim to deliver the IRQ vector directly
into the core on an interrupt (via the SPR EPR) rather than having
to go IACK on the PIC. This is suppose to provide an improvment
in interrupt latency by reducing the time to get the IRQ vector.
Signed-off-by: Kumar Gala
