This version is rebased on top of Gavin's patches of EEH support for guest and related fixes which are supposed to be merged in 3.17.
Changed from v1: * Don't overwrite PE flags * Don't return segment alignment if M64 is not supported * Output M64 total size and segment size together with M32 and IO Currently, all MMIO resources, including 64-bits MMIO resources are hooked to PHB 32-bits MMIO BAR, which has limited space. If there're PCI devices with large 64-bits MMIO BAR (could reach 1GB), we're running out of MMIO resources (as well as PE numbers) quickly. The patchset reuses the M32 infrastructure to support M64: * The last M64 BAR covers all M64 aperatus and that's shared by all PEs. * Reuse ppc_md.pcibios_window_alignment() to affect resource assignment in PCI core so that we can get well segmented 64-bits window of PCI bridges. * One PCI bus might require multiple discrete M64 segment. We invent if we're going to unfreeze any one in the group. Gavin Shan (5): powerpc/powernv: Allow to freeze PE powerpc/powernv: Split ioda_eeh_get_state() powerpc/powernv: Handle compound PE powerpc/powernv: Handle compound PE for EEH powerpc/powernv: Handle compound PE in config accessors Guo Chao (1): powerpc/powernv: Enable M64 aperatus for PHB3 arch/powerpc/include/asm/opal.h | 17 +- arch/powerpc/platforms/powernv/eeh-ioda.c | 293 +++++++++------- arch/powerpc/platforms/powernv/opal-wrappers.S | 2 +- arch/powerpc/platforms/powernv/pci-ioda.c | 448 +++++++++++++++++++++++-- arch/powerpc/platforms/powernv/pci.c | 87 +++-- arch/powerpc/platforms/powernv/pci.h | 23 ++ 6 files changed, 694 insertions(+), 176 deletions(-) -- 1.9.1 _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev