Re: [PATCH v2 01/10] powerpc/perf: Add support for ISA3.1 PMU SPRs

> On 13-Jul-2020, at 6:20 PM, Michael Ellerman wrote: > > Athira Rajeev > writes: >>> On 08-Jul-2020, at 4:32 PM, Michael Ellerman wrote: >>> >>> Athira Rajeev writes: >>> ... diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/cor

Re: [PATCH v2 01/10] powerpc/perf: Add support for ISA3.1 PMU SPRs

Athira Rajeev writes: >> On 08-Jul-2020, at 4:32 PM, Michael Ellerman wrote: >> >> Athira Rajeev writes: >> ... >>> diff --git a/arch/powerpc/perf/core-book3s.c >>> b/arch/powerpc/perf/core-book3s.c >>> index cd6a742..5c64bd3 100644 >>> --- a/arch/powerpc/perf/core-book3s.c >>> +++ b/arch/powe

Re: [PATCH v2 01/10] powerpc/perf: Add support for ISA3.1 PMU SPRs

> On 08-Jul-2020, at 4:32 PM, Michael Ellerman wrote: > > Athira Rajeev writes: > ... >> diff --git a/arch/powerpc/perf/core-book3s.c >> b/arch/powerpc/perf/core-book3s.c >> index cd6a742..5c64bd3 100644 >> --- a/arch/powerpc/perf/core-book3s.c >> +++ b/arch/powerpc/perf/core-book3s.c >> @@

Re: [PATCH v2 01/10] powerpc/perf: Add support for ISA3.1 PMU SPRs

Athira Rajeev writes: ... > diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c > index cd6a742..5c64bd3 100644 > --- a/arch/powerpc/perf/core-book3s.c > +++ b/arch/powerpc/perf/core-book3s.c > @@ -39,10 +39,10 @@ struct cpu_hw_events { > unsigned int flags[MAX_HWE

[PATCH v2 01/10] powerpc/perf: Add support for ISA3.1 PMU SPRs

From: Madhavan Srinivasan PowerISA v3.1 includes new performance monitoring unit(PMU) special purpose registers (SPRs). They are Monitor Mode Control Register 3 (MMCR3) Sampled Instruction Event Register 2 (SIER2) Sampled Instruction Event Register 3 (SIER3) MMCR3 is added for further sampling