On Fri, 01 Sep 2017 19:39:41 +1000
Michael Ellerman wrote:
> Nicholas Piggin writes:
>
> > On Wed, 30 Aug 2017 21:25:59 +1000
> > Michael Ellerman wrote:
> >
> >> Nicholas Piggin writes:
> >>
> >> > When
Nicholas Piggin writes:
> On Wed, 30 Aug 2017 21:25:59 +1000
> Michael Ellerman wrote:
>
>> Nicholas Piggin writes:
>>
>> > When stop is executed with EC=ESL=0, it appears to execute like a
>> > normal instruction (resuming from NIP
On Wed, 30 Aug 2017 21:25:59 +1000
Michael Ellerman wrote:
> Nicholas Piggin writes:
>
> > When stop is executed with EC=ESL=0, it appears to execute like a
> > normal instruction (resuming from NIP when woken by interrupt).
> > So all the save/restore
Nicholas Piggin writes:
> When stop is executed with EC=ESL=0, it appears to execute like a
> normal instruction (resuming from NIP when woken by interrupt).
> So all the save/restore handling can be avoided completely. In
> particular NV GPRs do not have to be saved, and MSR
On Tue, 29 Aug 2017 10:20:48 +1000
Paul Mackerras wrote:
> On Fri, Aug 25, 2017 at 02:30:36PM +1000, Nicholas Piggin wrote:
> > When stop is executed with EC=ESL=0, it appears to execute like a
> > normal instruction (resuming from NIP when woken by interrupt).
> > So all the
On Fri, Aug 25, 2017 at 02:30:36PM +1000, Nicholas Piggin wrote:
> When stop is executed with EC=ESL=0, it appears to execute like a
> normal instruction (resuming from NIP when woken by interrupt).
> So all the save/restore handling can be avoided completely. In
> particular NV GPRs do not have
When stop is executed with EC=ESL=0, it appears to execute like a
normal instruction (resuming from NIP when woken by interrupt).
So all the save/restore handling can be avoided completely. In
particular NV GPRs do not have to be saved, and MSR does not have
to be switched back to kernel MSR.
So