Re: [PATCH v3 4/4] powerpc/64s: idle ESL=0 stop can avoid MSR and save/restore overhead

2017-09-20 Thread Nicholas Piggin
On Fri, 01 Sep 2017 19:39:41 +1000 Michael Ellerman wrote: > Nicholas Piggin writes: > > > On Wed, 30 Aug 2017 21:25:59 +1000 > > Michael Ellerman wrote: > > > >> Nicholas Piggin writes: > >> > >> > When

Re: [PATCH v3 4/4] powerpc/64s: idle ESL=0 stop can avoid MSR and save/restore overhead

2017-09-01 Thread Michael Ellerman
Nicholas Piggin writes: > On Wed, 30 Aug 2017 21:25:59 +1000 > Michael Ellerman wrote: > >> Nicholas Piggin writes: >> >> > When stop is executed with EC=ESL=0, it appears to execute like a >> > normal instruction (resuming from NIP

Re: [PATCH v3 4/4] powerpc/64s: idle ESL=0 stop can avoid MSR and save/restore overhead

2017-08-30 Thread Nicholas Piggin
On Wed, 30 Aug 2017 21:25:59 +1000 Michael Ellerman wrote: > Nicholas Piggin writes: > > > When stop is executed with EC=ESL=0, it appears to execute like a > > normal instruction (resuming from NIP when woken by interrupt). > > So all the save/restore

Re: [PATCH v3 4/4] powerpc/64s: idle ESL=0 stop can avoid MSR and save/restore overhead

2017-08-30 Thread Michael Ellerman
Nicholas Piggin writes: > When stop is executed with EC=ESL=0, it appears to execute like a > normal instruction (resuming from NIP when woken by interrupt). > So all the save/restore handling can be avoided completely. In > particular NV GPRs do not have to be saved, and MSR

Re: [PATCH v3 4/4] powerpc/64s: idle ESL=0 stop can avoid MSR and save/restore overhead

2017-08-28 Thread Nicholas Piggin
On Tue, 29 Aug 2017 10:20:48 +1000 Paul Mackerras wrote: > On Fri, Aug 25, 2017 at 02:30:36PM +1000, Nicholas Piggin wrote: > > When stop is executed with EC=ESL=0, it appears to execute like a > > normal instruction (resuming from NIP when woken by interrupt). > > So all the

Re: [PATCH v3 4/4] powerpc/64s: idle ESL=0 stop can avoid MSR and save/restore overhead

2017-08-28 Thread Paul Mackerras
On Fri, Aug 25, 2017 at 02:30:36PM +1000, Nicholas Piggin wrote: > When stop is executed with EC=ESL=0, it appears to execute like a > normal instruction (resuming from NIP when woken by interrupt). > So all the save/restore handling can be avoided completely. In > particular NV GPRs do not have

[PATCH v3 4/4] powerpc/64s: idle ESL=0 stop can avoid MSR and save/restore overhead

2017-08-24 Thread Nicholas Piggin
When stop is executed with EC=ESL=0, it appears to execute like a normal instruction (resuming from NIP when woken by interrupt). So all the save/restore handling can be avoided completely. In particular NV GPRs do not have to be saved, and MSR does not have to be switched back to kernel MSR. So