> From: Thomas Gleixner
> Sent: Friday, November 11, 2022 9:54 PM
>
> Enough of history and theory. Here comes part 1:
>
> This is just a cleanup and a reorganisation of the PCI/MSI code which
> became quite an unreadable mess over time. There is no intentional
> functional change in this
Hi!
This is a three part series which provides support for per device MSI
interrupt domains. This solves conceptual problems of the current PCI/MSI
design which are in the way of providing support for PCI/MSI[-X] and
the upcoming PCI/IMS mechanism on the same device.
IMS (Interrupt Message
