An external IRQ line would let you limit interrupts to rising edges
rather than all edges, though you'd lose the ability to
directly read the line status.
oh, one cannot read the IRQ line? didn't know that. Also I not sure
all Freescale CPUs can do rising edge.
I suspect that you may
David Laight david.lai...@aculab.com wrote on 2010/12/13 09:33:37:
An external IRQ line would let you limit interrupts to rising edges
rather than all edges, though you'd lose the ability to
directly read the line status.
oh, one cannot read the IRQ line? didn't know that. Also I
On Mon, 13 Dec 2010 11:32:00 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
David Laight david.lai...@aculab.com wrote on 2010/12/13 09:33:37:
An external IRQ line would let you limit interrupts to rising edges
rather than all edges, though you'd lose the ability to
Scott Wood scottw...@freescale.com wrote on 2010/12/13 18:33:56:
On Mon, 13 Dec 2010 11:32:00 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
David Laight david.lai...@aculab.com wrote on 2010/12/13 09:33:37:
An external IRQ line would let you limit interrupts to
On Mon, 13 Dec 2010 18:41:32 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Scott Wood scottw...@freescale.com wrote on 2010/12/13 18:33:56:
On Mon, 13 Dec 2010 11:32:00 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
What if one has several NAND chips to
Scott Wood scottw...@freescale.com wrote on 2010/12/13 18:51:31:
On Mon, 13 Dec 2010 18:41:32 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Scott Wood scottw...@freescale.com wrote on 2010/12/13 18:33:56:
On Mon, 13 Dec 2010 11:32:00 +0100
Joakim Tjernlund
On Mon, 13 Dec 2010 20:30:27 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Scott Wood scottw...@freescale.com wrote on 2010/12/13 18:51:31:
On Mon, 13 Dec 2010 18:41:32 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Scott Wood scottw...@freescale.com wrote
Scott Wood scottw...@freescale.com wrote on 2010/12/13 20:49:50:
On Mon, 13 Dec 2010 20:30:27 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Scott Wood scottw...@freescale.com wrote on 2010/12/13 18:51:31:
On Mon, 13 Dec 2010 18:41:32 +0100
Joakim Tjernlund
Scott Wood scottw...@freescale.com wrote on 2010/12/10 18:56:39:
On Fri, 10 Dec 2010 13:39:01 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Scott Wood scottw...@freescale.com wrote on 2010/12/08 23:25:59:
On Wed, 8 Dec 2010 17:02:45 -0500
Mark Mason
Scott,
do you think this issue also applies to MPC8377 ?
I'm in the middle of a small redesign for series production and would
like not to miss a thing.
We have Nand, Nor and MRAM connected to LBC.
Since RFS is running from NAND and we use the MRAM as a non-volatile
SRAM I'd like to avoid
Andre Schwarz andre.schw...@matrix-vision.de wrote on 2010/12/10 09:47:10:
Scott,
do you think this issue also applies to MPC8377 ?
Probably, I think this is so for all eLBC controllers.
I'm in the middle of a small redesign for series production and would
like not to miss a thing.
We
Scott Wood scottw...@freescale.com wrote on 2010/12/08 23:25:59:
On Wed, 8 Dec 2010 17:02:45 -0500
Mark Mason ma...@postdiluvian.org wrote:
I don't think that using a software NAND controller instead of the LBC
FCM mode is all that bad. Again, I haven't actually done it, so check
the
On Fri, 10 Dec 2010 13:39:01 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Scott Wood scottw...@freescale.com wrote on 2010/12/08 23:25:59:
On Wed, 8 Dec 2010 17:02:45 -0500
Mark Mason ma...@postdiluvian.org wrote:
I don't think that using a software NAND controller
On Mon, 6 Dec 2010 22:15:54 -0500
Mark Mason ma...@postdiluvian.org wrote:
A few months ago I ran into some performance problems involving
UBI/NAND erases holding other devices off the LBC on an MPC8315. I
found a solution for this, which worked well, at least with the
hardware I was
On Wed, 8 Dec 2010 08:59:49 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
On Mon, 6 Dec 2010 22:15:54 -0500
Mark Mason ma...@postdiluvian.org wrote:
A few months ago I ran into some performance problems involving
UBI/NAND erases holding other devices off the LBC on an
Scott Wood scottw...@freescale.com wrote on 2010/12/08 18:18:39:
On Wed, 8 Dec 2010 08:59:49 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
On Mon, 6 Dec 2010 22:15:54 -0500
Mark Mason ma...@postdiluvian.org wrote:
A few months ago I ran into some performance
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Scott Wood scottw...@freescale.com wrote on 2010/12/08 18:18:39:
On Wed, 8 Dec 2010 08:59:49 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
On Mon, 6 Dec 2010 22:15:54 -0500
Mark Mason ma...@postdiluvian.org
Mark Mason ma...@postdiluvian.org wrote on 2010/12/08 20:26:16:
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Scott Wood scottw...@freescale.com wrote on 2010/12/08 18:18:39:
On Wed, 8 Dec 2010 08:59:49 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
On Wed, 8 Dec 2010 20:57:03 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Mark Mason ma...@postdiluvian.org wrote on 2010/12/08 20:26:16:
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Scott Wood scottw...@freescale.com wrote on 2010/12/08 18:18:39:
On Wed,
Scott Wood scottw...@freescale.com wrote on 2010/12/08 20:59:28:
On Wed, 8 Dec 2010 20:57:03 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Mark Mason ma...@postdiluvian.org wrote on 2010/12/08 20:26:16:
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Scott
On Wed, 8 Dec 2010 21:11:08 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Scott Wood scottw...@freescale.com wrote on 2010/12/08 20:59:28:
On Wed, 8 Dec 2010 20:57:03 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Can you think of any workaround such as not
Scott Wood scottw...@freescale.com wrote on 2010/12/08 21:25:51:
On Wed, 8 Dec 2010 21:11:08 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Scott Wood scottw...@freescale.com wrote on 2010/12/08 20:59:28:
On Wed, 8 Dec 2010 20:57:03 +0100
Joakim Tjernlund
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Is there any risk that the NAND device will drive the LB and
corrupt the bus for other devices?
I think the only thing the NAND chip should be driving is the busy pin,
OK, good. What function is actually lost if one uses an GPIO
On Wed, 8 Dec 2010 22:26:59 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Scott Wood scottw...@freescale.com wrote on 2010/12/08 21:25:51:
On Wed, 8 Dec 2010 21:11:08 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Scott Wood scottw...@freescale.com wrote on
On Wed, 8 Dec 2010 17:02:45 -0500
Mark Mason ma...@postdiluvian.org wrote:
I don't think that using a software NAND controller instead of the LBC
FCM mode is all that bad. Again, I haven't actually done it, so check
the MTD docs, but I'm pretty sure the software is meant to do that, so
it
The problem cropped up when there was a lot of traffic to the NAND
(Samsung K9WAGU08U1B-PIB0), with the NAND being on the LBC along with
a video chip that needed constant and prompt attention.
What I would see is that, as the writes happened, the erases would
wind up batched and issued
David Laight david.lai...@aculab.com wrote:
The problem cropped up when there was a lot of traffic to the NAND
(Samsung K9WAGU08U1B-PIB0), with the NAND being on the LBC along with
a video chip that needed constant and prompt attention.
What I would see is that, as the writes happened,
On Mon, 6 Dec 2010 22:15:54 -0500
Mark Mason ma...@postdiluvian.org wrote:
A few months ago I ran into some performance problems involving
UBI/NAND erases holding other devices off the LBC on an MPC8315. I
found a solution for this, which worked well, at least with the
hardware I was working
Scott Wood scottw...@freescale.com wrote:
On Mon, 6 Dec 2010 22:15:54 -0500
Mark Mason ma...@postdiluvian.org wrote:
A few months ago I ran into some performance problems involving
UBI/NAND erases holding other devices off the LBC on an MPC8315. I
found a solution for this, which
On Tue, 7 Dec 2010 18:24:45 -0500
Mark Mason ma...@postdiluvian.org wrote:
Scott Wood scottw...@freescale.com wrote:
On Mon, 6 Dec 2010 22:15:54 -0500
Mark Mason ma...@postdiluvian.org wrote:
What I found, though, was that the NAND did not inherently assert BUSY
as part of the
A few months ago I ran into some performance problems involving
UBI/NAND erases holding other devices off the LBC on an MPC8315. I
found a solution for this, which worked well, at least with the
hardware I was working with. I suspect the same problem affects other
PPCs, probably including
31 matches
Mail list logo
