Re: MPC85xx External/Internal Interrupts

2009-09-10 Thread Sebastian Andrzej Siewior
* Scott Wood | 2009-09-09 13:28:57 [-0500]: That's why you always have an offset of 16 between every internal interupt source number in the MPC855ERM document and those weired numbers in the device tree :) This seems to be a common point of confusion -- we should probably put something in the

Re: MPC85xx External/Internal Interrupts

2009-09-10 Thread Sebastian Andrzej Siewior
* Sebastian Andrzej Siewior | 2009-09-10 15:15:44 [+0200]: * Scott Wood | 2009-09-09 13:28:57 [-0500]: That's why you always have an offset of 16 between every internal interupt source number in the MPC855ERM document and those weired numbers in the device tree :) something in the dts

Re: MPC85xx External/Internal Interrupts

2009-09-10 Thread Scott Wood
Sebastian Andrzej Siewior wrote: So the split is a FSL thing. What do you thing about making this clear? Adding into every .dts a comment right on top or maybe in Documentation/powerpc/dts-bindings/fsl/? Add an fsl/mpic.txt binding that describes this and any other pecularities above and

Re: MPC85xx External/Internal Interrupts

2009-09-09 Thread Scott Wood
On Sun, Sep 06, 2009 at 01:06:41PM +0200, Sebastian Andrzej Siewior wrote: irq_of_parse_and_map() creates a mapping between the hardware irq number as specified in the device tree and the linux number (virq) which is used within the linux api in request_irq() for instance.

Re: MPC85xx External/Internal Interrupts

2009-09-06 Thread Sebastian Andrzej Siewior
* Alemao | 2009-09-04 16:29:15 [-0300]: On Fri, Sep 4, 2009 at 4:28 PM, Alemaoxcarand...@gmail.com wrote: I've read some posts in the list, and about: irq_of_parse_and_map() irq_create_map() But Im still trying to understand MPC85xx TSEC1 dts. Gianfar driver is using request_irq(), and

Fwd: MPC85xx External/Internal Interrupts

2009-09-04 Thread Alemao
Hi all, In all MPC85xx DTS files I have seen this interrupt configuration for TSEC1: interrupts = 29 2 30 2 34 2; 29 - TSEC1 interrupt transmit 30 - TSEC1 interrupt receive 34 - TSEC1 interrupt error But in MPC8555RM, chapter 10.1.5.2 the numbers are these: 13 - TSEC1 interrupt transmit 14 -

MPC85xx External/Internal Interrupts

2009-09-04 Thread Alemao
Hi all, In all MPC85xx DTS files I have seen this interrupt configuration for TSEC1: interrupts = 29 2 30 2 34 2; 29 - TSEC1 interrupt transmit 30 - TSEC1 interrupt receive 34 - TSEC1 interrupt error But in MPC8555RM, chapter 10.1.5.2 the numbers are these: 13 - TSEC1 interrupt transmit 14 -

Re: MPC85xx External/Internal Interrupts

2009-09-04 Thread Alemao
I've read some posts in the list, and about: irq_of_parse_and_map() irq_create_map() But Im still trying to understand MPC85xx TSEC1 dts. Gianfar driver is using request_irq(), and request_irq() uses virtual irq, right? Thats why in dts all irqs for TSEC1 are offseted of 16? Manual | DTS

Re: MPC85xx External/Internal Interrupts

2009-09-04 Thread Alemao
On Fri, Sep 4, 2009 at 4:14 PM, Alemaoxcarand...@gmail.com wrote: I've read some posts in the list, and about: irq_of_parse_and_map() irq_create_map() But Im still trying to understand MPC85xx TSEC1 dts. Gianfar driver is using request_irq(), and request_irq() uses virtual irq, right?