On Thu, Jul 02, 2009 at 03:56:39PM -0600, Aaron Pace wrote:
Secondly, can you elaborate on how/when the reserved area could be
mapped into the TLB? I don't by any means lay claim to a complete
understanding of this area, but aside from a direct ioremap/mmap call,
how would this area get
Hello,
I wrote to this list quite some time ago concerning a board that has 2
gigs of ram mapped in at 0x0.. - 0x0.7fff., and a second 2
gigs of ram at 0x1.. - 0x1.7fff.. Kumar responded and
mentioned that this wasn't currently supported in the powerpc
architecture. I've
On Jul 2, 2009, at 3:11 PM, Aaron Pace wrote:
Hello,
I wrote to this list quite some time ago concerning a board that has 2
gigs of ram mapped in at 0x0.. - 0x0.7fff., and a second 2
gigs of ram at 0x1.. - 0x1.7fff.. Kumar responded and
mentioned that this wasn't
Aaron Pace wrote:
In MMU_init of arch/powerpc/mm/init_32.c, where the current code sets
lmb.memory.cnt to zero, I instead walk through the memory regions and
call lmb_reserve for each chunk of memory that lies in a 'hole'.
There are then some minor fixups to make sure that total_memory and
On Thu, Jul 2, 2009 at 3:14 PM, Scott Woodscottw...@freescale.com wrote:
Aaron Pace wrote:
In MMU_init of arch/powerpc/mm/init_32.c, where the current code sets
lmb.memory.cnt to zero, I instead walk through the memory regions and
call lmb_reserve for each chunk of memory that lies in a
