On Tue, Dec 04, 2007 at 11:04:18PM +1100, Michael Ellerman wrote:
> On Tue, 2007-12-04 at 18:34 +0800, Li Tony wrote:
> > I am not very sure about spin_lock influence.
> > But maybe somebody will change the virq_to_hw implementation.
> > I will take virq_to_hw instead.
>
> I mean the time to take
On Tue, 2007-12-04 at 18:34 +0800, Li Tony wrote:
> > From: Michael Ellerman [mailto:[EMAIL PROTECTED]
> > Sent: 2007年12月4日 13:38
> > To: Li Tony
> > Cc: Li Tony; Gala Kumar; linuxppc-dev
> > Subject: Re: [PATCH] Add IPIC MSI interrupt support
> >
> >
> -Original Message-
> From: Michael Ellerman [mailto:[EMAIL PROTECTED]
> Sent: 2007年12月4日 13:38
> To: Li Tony
> Cc: Li Tony; Gala Kumar; linuxppc-dev
> Subject: Re: [PATCH] Add IPIC MSI interrupt support
>
> On Mon, 2007-12-03 at 17:07 +0800, Li Li wrote:
&g
Yes. According to the PCI spec, a PCI device can request multi MSI
interrupts and require that interrupts are consecutive.
But it is ok if only allocate one to it.
Anyway, the hwirq should be allocated from bitmap instead of increment
by hand.
I will correct this and resend the patch.
- Tony
On
> I'm not sure what you mean? For MSI there is only one MSI per device,
> but this code is used also for MSI-X which supports > 1 MSI per device.
Or more specifically, for MSI, -linux- supports only one per device (in
theory, it's possible to have multiple MSI non-X but it's a mess).
> Either way
On Mon, 2007-12-03 at 17:07 +0800, Li Li wrote:
> Hi Michael,
>
> I emulate mpic to write this IPIC MSI routines. :)
>
>
> > > diff --git a/arch/powerpc/platforms/83xx/mpc837x_mds.c
> > > b/arch/powerpc/platforms/83xx/mpc837x_mds.c
> > > index 6048f1b..dbea34b 100644
> > > --- a/arch/powerpc/pl
On Tue, 2007-12-04 at 05:03 +0800, Benjamin Herrenschmidt wrote:
>
> On Mon, 2007-12-03 at 17:07 +0800, Li Li wrote:
> >
> > In IPIC, the 8 MSI interrupts is handled as level intrrupt.
> > I just provide a versatile in case it is changed.
>
> Level ? Are you sure ? MSIs are by definition edge
On Mon, 2007-12-03 at 17:07 +0800, Li Li wrote:
>
> In IPIC, the 8 MSI interrupts is handled as level intrrupt.
> I just provide a versatile in case it is changed.
Level ? Are you sure ? MSIs are by definition edge interrupts... Or do
you have some weird logic that asserts a level input until yo
Hi Michael,
I emulate mpic to write this IPIC MSI routines. :)
> > diff --git a/arch/powerpc/platforms/83xx/mpc837x_mds.c
> > b/arch/powerpc/platforms/83xx/mpc837x_mds.c
> > index 6048f1b..dbea34b 100644
> > --- a/arch/powerpc/platforms/83xx/mpc837x_mds.c
> > +++ b/arch/powerpc/platforms/83xx/m
On Mon, 2007-12-03 at 09:52 +0800, David Gibson wrote:
> On Fri, Nov 30, 2007 at 11:48:39AM +0800, Li Li wrote:
> > The IPIC MSI is introduced on MPC837x chip.
> > Implements the IPIC MSI as two level interrupt controller.
> >
> > Signed-off-by: Tony Li <[EMAIL PROTECTED]>
> > ---
> > arch/p
Hi r64360,
A few comments below :)
On Fri, 2007-11-30 at 11:48 +0800, Li Li wrote:
> The IPIC MSI is introduced on MPC837x chip.
> Implements the IPIC MSI as two level interrupt controller.
>
> Signed-off-by: Tony Li <[EMAIL PROTECTED]>
> ---
> arch/powerpc/boot/dts/mpc8377_mds.dts | 14 +
On Fri, Nov 30, 2007 at 11:48:39AM +0800, Li Li wrote:
> The IPIC MSI is introduced on MPC837x chip.
> Implements the IPIC MSI as two level interrupt controller.
>
> Signed-off-by: Tony Li <[EMAIL PROTECTED]>
> ---
> arch/powerpc/boot/dts/mpc8377_mds.dts | 14 ++
> arch/powerpc/boot/dts/mpc
12 matches
Mail list logo
