On 09/11/2012 12:06 PM, Caraman Mihai Claudiu-B02008 wrote:
>> diff --git a/arch/powerpc/mm/tlb_low_64e.S
>> b/arch/powerpc/mm/tlb_low_64e.S
>> index efe0f33..8e82772 100644
>> --- a/arch/powerpc/mm/tlb_low_64e.S
>> +++ b/arch/powerpc/mm/tlb_low_64e.S
>> @@ -232,6 +232,173 @@ itlb_miss_fault_bolted
> diff --git a/arch/powerpc/mm/tlb_low_64e.S
> b/arch/powerpc/mm/tlb_low_64e.S
> index efe0f33..8e82772 100644
> --- a/arch/powerpc/mm/tlb_low_64e.S
> +++ b/arch/powerpc/mm/tlb_low_64e.S
> @@ -232,6 +232,173 @@ itlb_miss_fault_bolted:
> beq tlb_miss_common_bolted
> b itlb_miss
On 09/07/2012 06:50 PM, Benjamin Herrenschmidt wrote:
> #endif /* CONFIG_PPC64 */
> @@ -377,7 +382,7 @@ void tlb_flush_pgtable(struct mmu_gather *tlb,
> unsigned long address)
> {
> int tsize = mmu_psize_defs[mmu_pte_psize].enc;
>
> - if (book3e_htw_enabled) {
>>>
On Fri, 2012-06-15 at 11:05 +1000, Benjamin Herrenschmidt wrote:
> > -#define MMU_PAGE_COUNT 14
> > +#define MMU_PAGE_2M 6
> > +#define MMU_PAGE_4M 7
> > +#define MMU_PAGE_8M 8
> > +#define MMU_PAGE_16M 9
> > +#define MMU_PAGE_64M 10
> > +#define MMU_PAGE_256M11
> > +#define MMU_PA
On Fri, 2012-09-07 at 17:55 -0700, Nishanth Aravamudan wrote:
> On 08.09.2012 [09:50:04 +1000], Benjamin Herrenschmidt wrote:
>
> > BTW. On another note, can you pickup Ananth series for larger address
>
> I think you mean Aneesh here? Just to help Scott find the thread.
Ah yes, sorry, my bad.
On 08.09.2012 [09:50:04 +1000], Benjamin Herrenschmidt wrote:
> BTW. On another note, can you pickup Ananth series for larger address
I think you mean Aneesh here? Just to help Scott find the thread.
Thanks,
Nish
> space (minus the one patch that breaks the BookE build, it shouldn't
> matter) a
> That would be one more cache line that misses need... and the threads
> share cache, so there's no ping-pong.
Ok, keep it that way then.
> >> After all that, do you have some bullets left for the HW designers ?
>
> They seem to not care much about making our lives easier, only how bad
> the b
On 09/07/2012 02:34 PM, Scott Wood wrote:
> On 09/06/2012 11:41 PM, Benjamin Herrenschmidt wrote:
>>> diff --git a/arch/powerpc/include/asm/mmu-book3e.h
>>> b/arch/powerpc/include/asm/mmu-book3e.h
>>> index eeabcdb..3072aa0 100644
>>> --- a/arch/powerpc/include/asm/mmu-book3e.h
>>> +++ b/arch/powe
On Thu, 2012-06-14 at 18:41 -0500, Scott Wood wrote:
> There are a few things that make the existing hw tablewalk handlers
> unsuitable for e6500:
>
> - Indirect entries go in TLB1 (though the resulting direct entries go in
>TLB0).
>
> - It has threads, but no "tlbsrx." -- so we need a spin
On 06/14/2012 08:05 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2012-06-14 at 18:41 -0500, Scott Wood wrote:
>> - Like on e5500, the linear mapping is bolted, so we don't need the
>>overhead of supporting nested tlb misses.
>>
>> Note that hardware tablewalk does not work in rev1 of e6500.
>>
On Fri, 2012-06-15 at 11:50 -0500, Scott Wood wrote:
> On 06/14/2012 08:05 PM, Benjamin Herrenschmidt wrote:
> >> - It has threads, but no "tlbsrx." -- so we need a spinlock and
> >>a normal "tlbsx". Because we need this lock, hardware tablewalk
> >>is mandatory on e6500 unless we want to
On 06/14/2012 08:05 PM, Benjamin Herrenschmidt wrote:
>> - It has threads, but no "tlbsrx." -- so we need a spinlock and
>>a normal "tlbsx". Because we need this lock, hardware tablewalk
>>is mandatory on e6500 unless we want to add spinlock+tlbsx to
>>the normal bolted TLB miss handl
On Thu, 2012-06-14 at 18:41 -0500, Scott Wood wrote:
> There are a few things that make the existing hw tablewalk handlers
> unsuitable for e6500:
>
> - Indirect entries go in TLB1 (though the resulting direct entries go in
>TLB0).
That per-se doesn't justify a whole new handler... patching
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