On Wed, Sep 04, 2019 at 01:23:36PM +1000, Alastair D'Silva wrote:
> > Maybe also add "msr" in the clobbers.
> >
> Ok.
There is no known register "msr" in GCC.
Segher
On Tue, 2019-09-03 at 22:11 +0200, Gabriel Paubert wrote:
> On Tue, Sep 03, 2019 at 01:31:57PM -0500, Segher Boessenkool wrote:
> > On Tue, Sep 03, 2019 at 07:05:19PM +0200, Christophe Leroy wrote:
> > > Le 03/09/2019 à 18:04, Segher Boessenkool a écrit :
> > > > (Why are they separate though? It
On Tue, 2019-09-03 at 11:04 -0500, Segher Boessenkool wrote:
> On Tue, Sep 03, 2019 at 04:28:09PM +0200, Christophe Leroy wrote:
> > Le 03/09/2019 à 15:04, Segher Boessenkool a écrit :
> > > On Tue, Sep 03, 2019 at 03:23:57PM +1000, Alastair D'Silva wrote:
> > > > + asm volatile(
> > > > +
On Tue, 2019-09-03 at 08:08 +0200, Christophe Leroy wrote:
>
> Le 03/09/2019 à 07:23, Alastair D'Silva a écrit :
> > From: Alastair D'Silva
> >
> > Similar to commit 22e9c88d486a
> > ("powerpc/64: reuse PPC32 static inline flush_dcache_range()")
> > this patch converts the following ASM symbols
On Tue, Sep 03, 2019 at 01:31:57PM -0500, Segher Boessenkool wrote:
> On Tue, Sep 03, 2019 at 07:05:19PM +0200, Christophe Leroy wrote:
> > Le 03/09/2019 à 18:04, Segher Boessenkool a écrit :
> > >(Why are they separate though? It could just be one loop var).
> >
> > Yes it could just be a single
On Tue, Sep 03, 2019 at 07:05:19PM +0200, Christophe Leroy wrote:
> Le 03/09/2019 à 18:04, Segher Boessenkool a écrit :
> >(Why are they separate though? It could just be one loop var).
>
> Yes it could just be a single loop var, but in that case it would have
> to be reset at the start of the s
Le 03/09/2019 à 18:04, Segher Boessenkool a écrit :
On Tue, Sep 03, 2019 at 04:28:09PM +0200, Christophe Leroy wrote:
Le 03/09/2019 à 15:04, Segher Boessenkool a écrit :
On Tue, Sep 03, 2019 at 03:23:57PM +1000, Alastair D'Silva wrote:
+ asm volatile(
+ " mtctr %2;"
+
On Tue, Sep 03, 2019 at 04:28:09PM +0200, Christophe Leroy wrote:
> Le 03/09/2019 à 15:04, Segher Boessenkool a écrit :
> >On Tue, Sep 03, 2019 at 03:23:57PM +1000, Alastair D'Silva wrote:
> >>+ asm volatile(
> >>+ " mtctr %2;"
> >>+ " mtmsr %3;"
> >>+ " isync;
Le 03/09/2019 à 15:04, Segher Boessenkool a écrit :
Hi!
On Tue, Sep 03, 2019 at 03:23:57PM +1000, Alastair D'Silva wrote:
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
+#if !defined(CONFIG_PPC_8xx) & !defined(CONFIG_PPC64)
Please write that as &&? That is more usual, and t
Hi!
On Tue, Sep 03, 2019 at 03:23:57PM +1000, Alastair D'Silva wrote:
> diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
> +#if !defined(CONFIG_PPC_8xx) & !defined(CONFIG_PPC64)
Please write that as &&? That is more usual, and thus, easier to read.
> +static void flush_dcache_icache_
Christophe Leroy writes:
> Le 03/09/2019 à 07:23, Alastair D'Silva a écrit :
>> From: Alastair D'Silva
>>
>> Similar to commit 22e9c88d486a
>> ("powerpc/64: reuse PPC32 static inline flush_dcache_range()")
>> this patch converts the following ASM symbols to C:
>> flush_icache_range()
>>
Le 03/09/2019 à 07:23, Alastair D'Silva a écrit :
From: Alastair D'Silva
Similar to commit 22e9c88d486a
("powerpc/64: reuse PPC32 static inline flush_dcache_range()")
this patch converts the following ASM symbols to C:
flush_icache_range()
__flush_dcache_icache()
__flush_dcach
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