Hi Ira,
On 01/25/2011 06:29 PM, Ira W. Snyder wrote:
On Tue, Jan 25, 2011 at 04:32:02PM +0200, Felix Radensky wrote:
Hi Ira,
On 01/25/2011 02:18 AM, Ira W. Snyder wrote:
On Tue, Jan 25, 2011 at 01:39:39AM +0200, Felix Radensky wrote:
Hi Ira, Scott
On 01/25/2011 12:26 AM, Ira W. Snyder
On Thu, Jan 27, 2011 at 10:32:19AM +0200, Felix Radensky wrote:
Hi Ira,
On 01/25/2011 06:29 PM, Ira W. Snyder wrote:
On Tue, Jan 25, 2011 at 04:32:02PM +0200, Felix Radensky wrote:
Hi Ira,
On 01/25/2011 02:18 AM, Ira W. Snyder wrote:
On Tue, Jan 25, 2011 at 01:39:39AM +0200, Felix
What was the ppc you used?
The 8315E PowerQUIICC II
On 85xx/QorIQ-family chips such as P2020, there is no DMA controller
inside the PCIe controller itself (or are you talking about bus
mastering by the PCIe device[1]? interface is a bit ambiguous),
though it was considered part of the
On Wed, 26 Jan 2011 10:18:01 +
David Laight david.lai...@aculab.com wrote:
What was the ppc you used?
The 8315E PowerQUIICC II
Ah. The interconnect between the DMA engine and PCIe is different on
83xx.
The DMA engine and PCIe are both on OCeaN, so the traffic
does not need to
I'm trying to use FSL DMA engine to perform DMA transfer from
memory buffer obtained by kmalloc() to PCI memory. This is on
custom board based on P2020 running linux-2.6.35. The PCI
device is Altera FPGA, connected directly to SoC PCI-E controller.
You'll need to use the dma engine that is
Hi Ira,
On 01/25/2011 02:18 AM, Ira W. Snyder wrote:
On Tue, Jan 25, 2011 at 01:39:39AM +0200, Felix Radensky wrote:
Hi Ira, Scott
On 01/25/2011 12:26 AM, Ira W. Snyder wrote:
On Mon, Jan 24, 2011 at 11:47:22PM +0200, Felix Radensky wrote:
Hi,
I'm trying to use FSL DMA engine to perform
On Tue, Jan 25, 2011 at 04:32:02PM +0200, Felix Radensky wrote:
Hi Ira,
On 01/25/2011 02:18 AM, Ira W. Snyder wrote:
On Tue, Jan 25, 2011 at 01:39:39AM +0200, Felix Radensky wrote:
Hi Ira, Scott
On 01/25/2011 12:26 AM, Ira W. Snyder wrote:
On Mon, Jan 24, 2011 at 11:47:22PM +0200,
custom board based on P2020 running linux-2.6.35. The PCI
device is Altera FPGA, connected directly to SoC PCI-E
controller.
This sounds like your FPGA doesn't handle burst mode accesses
correctly.
A logic analyzer will help you prove it.
He is doing PCIe, not PCI.
A PCIe transfers
On Tue, 25 Jan 2011 16:34:49 +
David Laight david.lai...@aculab.com wrote:
custom board based on P2020 running linux-2.6.35. The PCI
device is Altera FPGA, connected directly to SoC PCI-E
controller.
This sounds like your FPGA doesn't handle burst mode accesses
On Mon, 24 Jan 2011 23:47:22 +0200
Felix Radensky fe...@embedded-sol.com wrote:
static int dma_transfer(struct dma_chan *chan, void *dst, void *src,
size_t len)
{
int rc = 0;
dma_addr_t dma_src;
dma_addr_t dma_dst;
dma_cookie_t cookie;
struct completion cmp;
On Mon, Jan 24, 2011 at 11:47:22PM +0200, Felix Radensky wrote:
Hi,
I'm trying to use FSL DMA engine to perform DMA transfer from
memory buffer obtained by kmalloc() to PCI memory. This is on
custom board based on P2020 running linux-2.6.35. The PCI
device is Altera FPGA, connected directly
Hi Ira, Scott
On 01/25/2011 12:26 AM, Ira W. Snyder wrote:
On Mon, Jan 24, 2011 at 11:47:22PM +0200, Felix Radensky wrote:
Hi,
I'm trying to use FSL DMA engine to perform DMA transfer from
memory buffer obtained by kmalloc() to PCI memory. This is on
custom board based on P2020 running
On Tue, Jan 25, 2011 at 01:39:39AM +0200, Felix Radensky wrote:
Hi Ira, Scott
On 01/25/2011 12:26 AM, Ira W. Snyder wrote:
On Mon, Jan 24, 2011 at 11:47:22PM +0200, Felix Radensky wrote:
Hi,
I'm trying to use FSL DMA engine to perform DMA transfer from
memory buffer obtained by
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