On Mon, 2013-08-26 at 21:49 -0500, Tang Yuantian-B29983 wrote:
+ };
+ pll1: pll1@820 {
+ #clock-cells = 1;
+ reg = 0x820;
+ compatible = fsl,core-pll-clock;
+
: Re: [v3] powerpc/mpc85xx: Update the clock device tree nodes
On Mon, 2013-08-26 at 21:49 -0500, Tang Yuantian-B29983 wrote:
+ };
+ pll1: pll1@820 {
+ #clock-cells = 1;
+ reg = 0x820
On Sun, 2013-08-25 at 21:42 -0500, Tang Yuantian-B29983 wrote:
clockgen: global-utilities@e1000 {
- compatible = fsl,b4420-clockgen, fsl,qoriq-clockgen-2.0;
+ compatible = fsl,b4420-clockgen, fsl,qoriq-clockgen-2.0,
+fixed-clock;
+
+ };
+ pll1: pll1@820 {
+ #clock-cells = 1;
+ reg = 0x820;
+ compatible = fsl,core-pll-clock;
+ clocks = clockgen;
+
clockgen: global-utilities@e1000 {
- compatible = fsl,b4420-clockgen, fsl,qoriq-clockgen-2.0;
+ compatible = fsl,b4420-clockgen, fsl,qoriq-clockgen-2.0,
+ fixed-clock;
+ clock-output-names = sysclk;
+
On Thu, Jun 06, 2013 at 09:06:51AM +0800, tang yuantian wrote:
From: Tang Yuantian yuantian.t...@freescale.com
The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
Signed-off-by: Li Yang
