On Jul 16, 2008, at 4:41 PM, Benjamin Herrenschmidt wrote:
On Wed, 2008-07-16 at 15:57 -0500, Kumar Gala wrote:
This makes sense. I think we need to order the stores in set_pte_at
regardless of CONFIG_SMP.
Nah, that shouldn't be necessary.
Yeah I finally came to that realization.
Also,
On Wed, 2008-07-16 at 15:57 -0500, Kumar Gala wrote:
> This makes sense. I think we need to order the stores in set_pte_at
> regardless of CONFIG_SMP.
Nah, that shouldn't be necessary.
> Also, I think we should change pte_clear to
> use pte_update() so we only clear the low-order flag bits
On Jul 16, 2008, at 3:57 PM, Kumar Gala wrote:
* 64-bit PTEs and reader vs writer hazards. How do we ensure that
the
TLB miss handler samples a consistent view of the pte. pte_updates
seem ok since we only update the flag word. However set_pte_at
seems
like it could be problematic.
ei
* 64-bit PTEs and reader vs writer hazards. How do we ensure that
the
TLB miss handler samples a consistent view of the pte. pte_updates
seem ok since we only update the flag word. However set_pte_at seems
like it could be problematic.
eieio on the writer and a data dependency on the reader
