Hi,
In arch/powerpc/kernel/head_44x.S file, it says it clears all the TLBs
except the current working one. In our case we have mainly 3 TLBs for
FLASH, SRAM and the UART. We have the TLB of 16MB of SRAM *which is
our total memory*. So the TLBs that we create from our bootloader will
be used for
Hi Wolfgang,
The link says about the initialization of the SDRAM; Does it
applicable in our case, where we have SRAM on our board. Does the
initialization means just clearing the memory in case of SRAM ? We
tried clearing the memory before the operation which doesnt work too.
We are creating a
We ported the uboot Memory test and tested the 15MB ram and it was
successful.interestingly we have only 16MB SRAM in our board.We used 1
MB of RAM for the bootloader to execute and tested the other 15 MB.
i couldnt see any reason why the DEAR, MSR value become identical.
checked the objcopy of my
Dear Vineeth _,
In message a9b543570910090320t1444f8f1qf4c8ab7dbbef6...@mail.gmail.com you
wrote:
We ported the uboot Memory test and tested the 15MB ram and it was
successful.interestingly we have only 16MB SRAM in our board.We used 1
Such a memory test means nothing. The only thing you can
It's seems a RAM initialize problem. Try to use ICE or your bootloader
to test initialized RAM wirh write/read operation.
Ex, use mtest in uboot to check memory. For ICE, it should be an
detailed memory test function like hardware diagnostic.
2009/9/24 Benjamin Herrenschmidt
I am trying to port linux on IBM powerpc-440x5. I have this board
which has this processor, a 16MB SRAM sits on location 0x0, uart and a
flash.I have a simple bootloader which does the following.
1. Initialize the processor (as part of it, we Generates the tlbs
for UART,16MB flash,16MB SRAM)
On Wed, 2009-09-23 at 20:19 +0530, Vineeth _ wrote:
I am trying to port linux on IBM powerpc-440x5. I have this board
which has this processor, a 16MB SRAM sits on location 0x0, uart and a
flash.I have a simple bootloader which does the following.
1. Initialize the processor (as part of
