Hi,
In arch/powerpc/kernel/head_44x.S file, it says it clears all the TLBs
except the current working one. In our case we have mainly 3 TLBs for
FLASH, SRAM and the UART. We have the TLB of 16MB of SRAM *which is
our total memory*. So the TLBs that we create from our bootloader will
be used for
* Andi Kleen a...@firstfloor.org [2009-10-14 09:18:38]:
How about something like this..
If the arch does not enable CONFIG_CPU_IDLE, the cpuidle_idle_call
which is called from cpu_idle() should call default_idle without
involving the registering cpuidle steps. This should prevent bloating
From: Akinobu Mita akinobu.m...@gmail.com
Subject: Fix
bitmap-introduce-bitmap_set-bitmap_clear-bitmap_find_next_zero_area.patch
- Rewrite bitmap_set and bitmap_clear
Instead of setting or clearing for each bit.
- Fix off-by-one errors in bitmap_find_next_zero_area
This bug was derived
On Thu, 2009-10-15 at 07:42 +0200, Joakim Tjernlund wrote:
I didn't say that, did I? More like:
if I don't do tlbil_va at all I get a lot of extra/duplicate TLB
errors
for the same address. Adding the patch makes these go away.
I guess one could do tlbil_va unconditionally but I didn't
see
Hi Linus !
A tad late due mostly to me being on vacation :-) Here's some powerpc
fixes for 2.6.32, not that much and nothing really big.
The following changes since commit 80f506918fdaaca6b574ba931536a58ce015c7be:
Linus Torvalds (1):
Merge branch 'for-linus' of
This patch disables the use of DMA_INTERRUPT capability with Async_tx
The fsldma produces a null transfer with DMA_INTERRUPT
capability when used with Async_tx. When RAID devices queue
a transaction via Async_tx, this results in a hang.
Signed-off-by: Vishnu Suresh vis...@freescale.com
---
Expose Talitos's XOR functionality to be used for
RAID Parity calculation via the Async_tx layer.
Thanks to Surender Kumar and Lee Nipper for their help in
realising this driver
Signed-off-by: Kim Phillips kim.phill...@freescale.com
Signed-off-by: Dipen Dudhat dipen.dud...@freescale.com
Hollis Blanchard holl...@us.ibm.com 15.10.09 00:57
On Fri, 2009-10-09 at 12:14 -0700, Hollis Blanchard wrote:
Rusty's version of BUILD_BUG_ON() does indeed fix the build break, and
also exposes the bug in kvmppc_account_exit_stat(). So to recap:
original: built but didn't work
Jan's:
The ioctl is only used for powermac systems and reads a partition
number from an array which is initialized at boot time way before the
nvram code is initialized. So it's safe to switch to unlocked_ioctl.
Signed-off-by: Thomas Gleixner t...@linutronix.de
Cc: Benjamin Herrenschmidt
Ben,
while looking at the ioctl in nvram_64.c I noticed a couple of issues
which are addressed by the folling patch series.
Thanks,
tglx
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nvram_find_partition() has no user. The call site was removed in the
arch/powerpc move, but the function stayed. Remove it.
Signed-off-by: Thomas Gleixner t...@linutronix.de
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: linuxppc-...@ozlabs.org
---
arch/powerpc/include/asm/nvram.h |
nvram_clear_error_log() calls ppc_md.nvram_write() even when
nvram_error_log_index is -1 (invalid). The nvram_write() function does
not check for a negative offset.
Check nvram_error_log_index as the other nvram log functions do.
Signed-off-by: Thomas Gleixner t...@linutronix.de
Cc: Benjamin
Mark all functions which are only called from nvram_init() __init.
Signed-off-by: Thomas Gleixner t...@linutronix.de
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: linuxppc-...@ozlabs.org
---
arch/powerpc/kernel/nvram_64.c | 14 +++---
1 file changed, 7 insertions(+), 7
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separaly as linux mm don't.
---
arch/powerpc/mm/fault.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index
Now updated with Scott's remarks.
There is still(probably) a trivial conflict in pte-8xx.h
Joakim Tjernlund (8):
8xx: invalidate non present TLBs
8xx: Update TLB asm so it behaves as linux mm expects.
8xx: Tag DAR with 0x00f0 to catch buggy instructions.
8xx: Fixup DAR from buggy dcbX
This is an assembler version to fixup DAR not being set
by dcbX, icbi instructions. There are two versions, one
uses selfmodifing code, the other uses a
jump table but is much bigger(default).
---
arch/powerpc/kernel/head_8xx.S | 180 +++-
1 files changed, 176
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they
cause a DTLB Error. Dectect this by tagging DAR with 0x00f0
at every exception exit that modifies DAR.
Test for DAR=0x00f0 in DataTLBError and bail
to handle_page_fault().
---
arch/powerpc/kernel/head_8xx.S | 15 ++-
1 files
Update the TLB asm to make proper use of _PAGE_DIRY and _PAGE_ACCESSED.
Get rid of _PAGE_HWWRITE too.
Pros:
- I/D TLB Miss never needs to write to the linux pte.
- _PAGE_ACCESSED is only set on TLB Error fixing accounting
- _PAGE_DIRTY is mapped to 0x100, the changed bit, and is set directly
Now that 8xx can fixup dcbX instructions, start using them
where possible like every other PowerPc arch do.
---
arch/powerpc/kernel/misc_32.S | 18 --
arch/powerpc/lib/copy_32.S| 24
2 files changed, 0 insertions(+), 42 deletions(-)
diff --git
There is no need to do set the DIRTY bit directly in DTLB Error.
Trap to do_page_fault() and let the generic MM code do the work.
---
arch/powerpc/kernel/head_8xx.S | 96
1 files changed, 0 insertions(+), 96 deletions(-)
diff --git
only DTLB Miss did set this bit, DTLB Error needs too otherwise
the setting is lost when the page becomes dirty.
---
arch/powerpc/kernel/head_8xx.S | 13 ++---
1 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
8xx has not had WRITETHRU due to lack of bits in the pte.
After the recent rewrite of the 8xx TLB code, there are
two bits left. Use one of them to WRITETHRU.
Perhaps use the last SW bit to PAGE_SPECIAL or PAGE_FILE?
---
arch/powerpc/include/asm/pte-8xx.h |5 +++--
Hi Felix,
do you have CONFIG_NO_HZ defined ?
I've seen similar problems with powerpc + CONFIG_NO_HZ. In my case the low-level
do_write_buffer (cfi_cmdset_0002.c) timed out too early. See
http://lkml.org/lkml/2009/9/3/84
Maybe in your case it's the do_erase_chip timing out too early.
---
On our MPC8548 (latest die revision) based boards with 2 GByte DDR2 RAM we see
an stable kernel when
CONFIG_HIGHMEM is not set
In this case only the first 768 MB will be used (as reported by /proc/cpuinfo).
Tested with/without the RT-patches for 2.6.29.6(-rt23) and 2.6.31.2(-rt13)
kernels.
On Thu, 15 Oct 2009 08:26:15 +1100, Benjamin Herrenschmidt wrote:
On Wed, 2009-10-14 at 23:02 +0200, Jean Delvare wrote:
Hi all,
On Tue, 13 Oct 2009 11:49:48 +0200, Jean Delvare wrote:
I2C bus being setup too fast sounds more likely. It might be worth
adding an arbitrary delay after
Hello,
Where is the most current linux work for the Freescale MPC5121 cpu stored.
What I am specifically interested in at this time is the CAN and USB subsystems.
rg
kd
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Linuxppc-dev@lists.ozlabs.org
Am Mittwoch 14 Oktober 2009 23:53:46 schrieben Sie:
hvc_console_print() calls the HVC client driver's put_chars() callback
to write some characters to the console. If the callback returns 0, that
indicates that no characters were written (perhaps the output buffer is
full), but
On Thu, 2009-10-15 at 12:49 +0200, Jean Delvare wrote:
Oh. Well, if that was the case, we would see errors all the time, not
just during initialization, right? Or does the I2C clock frequency
change over time somehow?
No but maybe we are a bit on the limit of the device and some
registers take
In my opinion the best place is the BSP available on the MPC5121e page
on the Freescale site.
I actually use the kernel in the git repository here which is similar to
the BSP:
http://git.denx.de/?p=linux-2.6-denx.git;a=shortlog;h=refs/heads/ltib-mpc5121ads-20090602
or here:
Thank you Paul,
The kernel from the BSP on Freescale site is crashing on the CAN in my case
(might be a hardware bug).
I could not find the source for the kernel in the BSP or on the freescale site.
I had not looked at
-Original Message- From: Scott Wood [mailto:scottw...@freescale.com]
Because that would be three times the device trees to maintain, and a
source of user confusion.
I wonder which is more confusing for the user:
1. Choosing one of three dts files.
2. Having only one dts for his board,
Hi, Norbert
Norbert van Bolhuis wrote:
Hi Felix,
do you have CONFIG_NO_HZ defined ?
I've seen similar problems with powerpc + CONFIG_NO_HZ. In my case the
low-level
do_write_buffer (cfi_cmdset_0002.c) timed out too early. See
http://lkml.org/lkml/2009/9/3/84
Maybe in your case it's the
Hi,
I have a FPGA connected to a MPC8347 through localbus.
The following kernel oops occurs sometimes:
Unable to handle kernel paging request for data at address 0x7ddfecb0
Faulting instruction address: 0xc00145f4
Oops: Kernel access of bad area, sig: 11 [#1]
PREEMPT
Modules linked in: ath_pci
On Thu, 15 Oct 2009 22:19:19 +1100, Benjamin Herrenschmidt wrote:
On Thu, 2009-10-15 at 12:49 +0200, Jean Delvare wrote:
Oh. Well, if that was the case, we would see errors all the time, not
just during initialization, right? Or does the I2C clock frequency
change over time somehow?
No
Michael Ellerman wrote:
On Tue, 2009-10-13 at 13:13 -0500, Nathan Fontenot wrote:
This adds the capability to DLPAR add and remove memory from the kernel. The
Hi Nathan,
Sorry to only get around to reviewing version 3, time is a commodity in
short supply :)
Index:
Michael Ellerman wrote:
On Tue, 2009-10-13 at 13:14 -0500, Nathan Fontenot wrote:
This adds the capability to DLPAR add and remove CPUs from the kernel. The
creates two new files /sys/devices/system/cpu/probe and
/sys/devices/system/cpu/release to handle the DLPAR addition and removal of
CPUs
On Thu, Oct 15, 2009 at 01:05:47PM +0200, Christian Borntraeger wrote:
The fact that struct console-write returns void indicates that the console
layer is not interested in errors. We have two policies we can implement:
1. drop console messages if case of congestion but keep the system going
On Thu, Oct 15, 2009 at 02:19:30PM +0200, Richard Cochran wrote:
-Original Message- From: Scott Wood [mailto:scottw...@freescale.com]
Because that would be three times the device trees to maintain, and a
source of user confusion.
I wonder which is more confusing for the user:
1.
On Thu, 15 Oct 2009, Benjamin Herrenschmidt wrote:
For some weird reason, our gcc until 4.3 (fixed in 4.3) had the weird
idea that the alignment attribute should not be allowed to force an
alignment greater than 32k. If attempted, it would warn -and- crop the
alignment to 32k.
[...]
This has
Hi Ben.
Here are some OF and MPC5200 changes needed for 2.6.32. Mostly
defconfig updates and a couple of new board dts files.
Cheers,
g.
The following changes since commit 161291396e76e0832c08f617eb9bd364d1648148:
Linus Torvalds (1):
Linux 2.6.32-rc4
are available in the git
On Thu, 15 Oct 2009, Benjamin Herrenschmidt wrote:
What do you recommend I do ?
I can ban gcc 4.3 but that's a bit harsh :-)
Yeah, let's try to avoid that.
I know a few people that won't be happy to be unable to build newer
kernels with current distro gccs.
Or can do the above making
arch/powerpc/kernel/head_8xx.o: In function `FixupDAR':
/home/rfeany/src/lnxnm/linux-dev/arch/powerpc/kernel/head_8xx.S:576: undefined
reference to `DARfix'
With all of your patches applied I have this problem:
open(/proc/mounts, O_RDONLY) = 3
fstat64(0x3, 0x7fc6ad58)=
On Wed, Oct 14, 2009 at 7:00 PM, Stephen Rothwell s...@canb.auug.org.au wrote:
Hi Grant,
On Tue, 06 Oct 2009 22:29:57 -0600 Grant Likely grant.lik...@secretlab.ca
wrote:
Well, I've got to start somewhere...
So here goes. I've begun the work to merge and clean up the OF device
tree
Robert Jennings wrote:
@@ -110,6 +125,9 @@ static long cmm_alloc_pages(long nr)
cmm_dbg(Begin request for %ld pages\n, nr);
while (nr) {
+ if (atomic_read(hotplug_active))
+ break;
+
addr = __get_free_page(GFP_NOIO |
Dear =?ISO-8859-1?Q?K=E1ri_Dav=ED=F0sson?=,
In message 4ad70927.3030...@marel.com you wrote:
The kernel from the BSP on Freescale site is crashing on the CAN in my case
(might be a hardware bug).
I don;t think so. There are some problems in this code, for example
the clocks seem to be
Am Donnerstag 15 Oktober 2009 18:09:06 schrieb Scott Wood:
On Thu, Oct 15, 2009 at 01:05:47PM +0200, Christian Borntraeger wrote:
The fact that struct console-write returns void indicates that the
console layer is not interested in errors. We have two policies we can
implement:
1. drop
Christian Borntraeger wrote:
Hmmm, if we are ok with having both options, we should let the hvc backend
decide if it wants to drain or to discard.
If we just busy loop, it actually does not matter how we let hvc_console
react
on 0, as long as we adopt all backends to use that interface
Christian Borntraeger wrote:
Right. Looking at more drivers it seems that both ways (waiting and dropping)
are used.
Hmmm, if we are ok with having both options, we should let the hvc backend
decide if it wants to drain or to discard.
I'd say the dropping approach is quite undesirable
Am Donnerstag 15 Oktober 2009 20:57:45 schrieb Scott Wood:
Doing it in the backend requires the backend to know whether it's being
called for printk or for user I/O. In the latter case, we don't want to
spin, but rather wait for an IRQ (or poll with a timer if there's no IRQ).
Right. Now you
Christian Borntraeger wrote:
About the backends, there are some that spin until the text is delivered (e.g.
virtio) , others can drop (e.g. iucv is a connection oriented protocol and it
will (and has to) drop if there is no connection).
Sure, dropping due to not having a connection makes
Scott Wood wrote:
Felix Radensky wrote:
Yes, NAND and NOR are on the same local bus controller.
Maybe powerpc folks can provide some insight here.
Is it possible that simultaneous access to NOR and NAND
on MPC8536 can result in NAND timeouts ?
I've heard other reports of such problems with
Drop the bkl from nvram_llseek() as it obviously protects nothing. The
file offset is safe in essence.
The ioctl can be converted to unlocked_ioctl because it just calls
pmac_get_partition() which reads a value from an array which was
initialized at early boot time. No need for serialization.
On Thu, 2009-10-15 at 12:37 -0400, Tim Abbott wrote:
Just to make sure I understand the nature of the problem, is the
current
breakage that gcc 4.3 will _warn_ on any compilation units on ppc64
that
use __page_aligned data, or something worse?
The cropping is clearly a potential
Joakim Tjernlund wrote:
Now updated with Scott's remarks.
There is still(probably) a trivial conflict in pte-8xx.h
Joakim Tjernlund (8):
8xx: invalidate non present TLBs
8xx: Update TLB asm so it behaves as linux mm expects.
8xx: Tag DAR with 0x00f0 to catch buggy instructions.
8xx:
The kernel from the BSP on Freescale site is crashing on the CAN in my case
(might be a hardware bug).
I don;t think so. There are some problems in this code, for example
the clocks seem to be wrong. Not toi menthin that the whole code is
hoplessly old and without chance of ever being
Hi Grant,
On Thu, 15 Oct 2009 11:06:15 -0600 Grant Likely grant.lik...@secretlab.ca
wrote:
In the mean time, I've pushed out the current series with acked-bys
added to my git server. I think I'm ready for things to start going
into linux-next. Since this is the first time I've asked for a
On Thu, 2009-10-15 at 10:40 -0500, Nathan Fontenot wrote:
Michael Ellerman wrote:
On Tue, 2009-10-13 at 13:14 -0500, Nathan Fontenot wrote:
This adds the capability to DLPAR add and remove CPUs from the kernel. The
creates two new files /sys/devices/system/cpu/probe and
ppc 8270, kernel 2.6.21.7
I took the following steps:
In a system call function , say , sys_reboot, interrupt was disabled
by local_irq_disable.
Then , value at the address of 0xc50 was set to a value , say ,
0x1234. Code was like this :
sys_reboot()
{
local_irq_disable();
*(volatile
[ added Leo and Timur to the Cc ]
On Wed, Oct 14, 2009 at 11:41 PM, Vishnu Suresh vis...@freescale.com wrote:
This patch disables the use of DMA_INTERRUPT capability with Async_tx
The fsldma produces a null transfer with DMA_INTERRUPT
capability when used with Async_tx. When RAID devices
On Thu, Oct 15, 2009 at 5:38 PM, Stephen Rothwell s...@canb.auug.org.au wrote:
Hi Grant,
On Thu, 15 Oct 2009 11:06:15 -0600 Grant Likely grant.lik...@secretlab.ca
wrote:
In the mean time, I've pushed out the current series with acked-bys
added to my git server. I think I'm ready for
On Fri, 2009-10-16 at 09:12 +0800, wilbur.chan wrote:
static inline unsigned long local_irq_disable(void)
{
unsigned long flags, zero;
__asm__ __volatile__(li %1,0; lbz %0,%2(13); stb %1,%2(13)
: =r (flags), =r (zero)
: i (offsetof(struct paca_struct,
On Thu, 2009-10-15 at 13:57 -0500, Scott Wood wrote:
I'd say the dropping approach is quite undesirable (significant
potential for output loss unless the buffer is huge), unless there's
simply no way to safely spin. Hopefully there are no such backends, but
if there are perhaps we can have
Hi, Scott
Scott Wood wrote:
Scott Wood wrote:
Felix Radensky wrote:
Yes, NAND and NOR are on the same local bus controller.
Maybe powerpc folks can provide some insight here.
Is it possible that simultaneous access to NOR and NAND
on MPC8536 can result in NAND timeouts ?
I've heard other
2009/10/16, Benjamin Herrenschmidt b...@kernel.crashing.org:
On Fri, 2009-10-16 at 09:12 +0800, wilbur.chan wrote:
static inline unsigned long local_irq_disable(void)
{
unsigned long flags, zero;
__asm__ __volatile__(li %1,0; lbz %0,%2(13); stb %1,%2(13)
: =r (flags), =r
Currently, ordinary pages use one pagetable layout, and each different
hugepage size uses a slightly different variant layout. A number of
places which need to walk the pagetable must first check the slice map
to see what the pagetable layout then handle the various different
forms. New
Currently we have a fair bit of rather fiddly code to manage the
various kmem_caches used to store page tables of various levels. We
generally have two caches holding some combination of PGD, PUD and PMD
tables, plus several more for the special hugepage pagetables.
This patch cleans this all up
Currently each available hugepage size uses a slightly different
pagetable layout: that is, the bottem level table of pointers to
hugepages is a different size, and may branch off from the normal page
tables at a different level. Every hugepage aware path that needs to
walk the pagetables must
This patch separates the parts of hugetlbpage.c which are inherently
specific to the hash MMU into a new hugelbpage-hash64.c file.
Signed-off-by: David Gibson d...@au1.ibm.com
---
arch/powerpc/include/asm/hugetlb.h |3
arch/powerpc/mm/Makefile |5 -
The hugepage arch code provides a number of hook functions/macros
which mirror the functionality of various normal page pte access
functions. Various changes in the normal page accessors (in
particular BenH's recent changes to the handling of lazy icache
flushing and PAGE_EXEC) have caused the
This patch simplifies the logic used to initialize hugepages on
powerpc. The somewhat oddly named set_huge_psize() is renamed to
add_huge_page_size() and now does all necessary verification of
whether it's given a valid hugepage sizes (instead of just some) and
instantiates the generic hstate
Currently, hpte_need_flush() only correctly flushes the given address
for normal pages. Callers for hugepages are required to mask the
address themselves.
But hpte_need_flush() already looks up the page sizes for its own
reasons, so this is a rather silly imposition on the callers. This
patch
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