On Tue, Feb 23, 2010 at 12:55:51PM +1100, Anton Blanchard wrote:
Hi Mel,
I'm back but a bit vague. Am on painkillers for the bashing I gave
myself down the hills.
You're pretty much on the button here. Only one thread at a time enters
zone_reclaim. The others back off and try the next
Hi Ben,
The following set of patches fixes kernel stack reset issue and also
potential race conditions.
This fix should be applied in 2.6.33 stable tree onwards.
Problem description:
(1) Repeated offline/online operation on pseries with extended cede
processor feature will run over the kernel
Cpu hotplug (offline) without dlpar operation will place cpu
in cede state and the extended_cede_processor() function will
return when resumed.
Kernel stack pointer needs to be reset before
start_secondary() is called to continue the online operation.
Rearrange condition checks for better code readability and
prevention of possible race conditions when
preferred_offline_state can potentially change during the
execution of pseries_mach_cpu_die(). The patch will make
pseries_mach_cpu_die() put cpu in one
Remove debug printks in pseries_mach_cpu_die(). These are
noisy at runtime. Traceevents can be added to instrument this
section of code.
The following KERN_INFO printks are removed:
cpu 62 (hwid 62) returned from cede.
Decrementer value =
Anton Vorontsov wrote:
diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c
index 8bd3c9f..cccb409 100644
--- a/drivers/net/gianfar.c
+++ b/drivers/net/gianfar.c
@@ -2021,7 +2021,6 @@ static int gfar_start_xmit(struct sk_buff *skb, struct
net_device *dev)
}
/* setup
Hi Dan,
any chance this patch could be merged for 2.6.34 ?
Thanks,
Anatolij
On Fri, 5 Feb 2010 14:42:52 +0100
Anatolij Gustschin ag...@denx.de wrote:
From: Piotr Ziecik ko...@semihalf.com
Adds initial version of MPC512x DMA driver.
Only memory to memory transfers are currenly supported.
This patch renames GE Fanuc boards following the split-up of the GE Fanuc joint
venture. These boards are now made by GE Intelligent platorms.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_ppc9a.dts |4 ++--
arch/powerpc/boot/dts/gef_sbc310.dts
On Sun, 28 Feb 2010, Albert Herranz wrote:
The HCD_NO_COHERENT_MEM USB host controller driver flag can be enabled
to instruct the USB stack to avoid allocating coherent memory for USB
buffers.
This flag is useful to overcome some esoteric memory access restrictions
found in some platforms.
Another fix for the extended ptrace patches in the -next tree.
The handling of breakpoints and watchpoints is inconsistent. When a
breakpoint or watchpoint is hit, the interrupt handler is clearing the
proper bits in the dbcr* registers, but leaving the dac* and iac* registers
alone. The ptrace
On Mon, 1 Mar 2010, Mel Gorman wrote:
Christoph, how feasible would it be to allow parallel reclaimers in
__zone_reclaim() that back off at a rate depending on the number of
reclaimers?
Not too hard. Zone locking is there but there may be a lot of bouncing
cachelines if you run it
On the MPC5200B, select the baud rate prescaler as /4 by default to make very
high baud rates (e.g. 3 MBaud) accessible and to achieve a higher precision
for high baud rates in general. For baud rates below ~500 Baud, the code will
automatically fall back to the /32 prescaler. The original
Alan Stern wrote:
--- a/drivers/usb/core/hcd.c
+++ b/drivers/usb/core/hcd.c
@@ -1260,6 +1260,34 @@ static void hcd_free_coherent(struct usb_bus *bus,
dma_addr_t *dma_handle,
*dma_handle = 0;
}
+static int urb_needs_setup_dma_map(struct usb_hcd *hcd, struct urb *urb)
+{
+
I'm getting a bunch of these after I 'reboot' or 'poweroff'
several times.
Empty flash at 0x0056205c ends at 0x00562800
Empty flash at 0x00565334 ends at 0x00565800
Empty flash at 0x00576104 ends at 0x00576800
JFFS2 notice: (848) check_node_data: wrong data CRC
in data node at 0x00577034: read
These patches add support for the 476 core. The goal is to have a single
binary that will run on both 44x and 47x, but we still have some details to
work out. The biggest is that the L1 cache line size differs on the two
platforms, but it's currently a compile-time option.
The code was
powerpc/44x: break out cpu init code into stand-alone function
From: Dave Kleikamp sha...@linux.vnet.ibm.com
The 47x platform supports multiple cores and shares code with 44x.
Break out code that is common for initializing the primary and secondary
cpus into a function which can be called for
powerpc/booke: Add Stack Marking support to Booke Exception Prolog
From: Torez Smith lnxto...@linux.vnet.ibm.com
Signed-off-by: Torez Smith lnxto...@linux.vnet.ibm.com
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/kernel/head_booke.h |5 +
1 files changed, 5
powerpc/47x: Base ppc476 support
From: Dave Kleikamp sha...@linux.vnet.ibm.com
This patch adds the base support for the 476 processor. The code was
primarily written by Ben Herrenschmidt and Torez Smith, but I've been
maintaining it for a while.
The goal is to have a single binary that will
powerpc/476: add machine check handler for 47x core
From: Dave Kleikamp sha...@linux.vnet.ibm.com
The 47x core's MCSR varies from 44x, so it needs it's own machine check
handler.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/cputable.h |1 +
powerpc/4xx: Simple platform for the ISS 4xx simulator
From: Torez Smith lnxto...@linux.vnet.ibm.com
This is a trivial 4xx plaform that uses the new simple bsp from
Josh and is handy to use in simulators such as ISS or even Mambo
who don't properly implement most of the actual devices in the
SoC
powerpc/476: Add isync after loading mmu and debug spr's
From: Dave Kleikamp sha...@linux.vnet.ibm.com
476 requires an isync after loading MMU and debug related SPR's. Some of
these are in performance-critical paths and may need to be optimized, but
initially, we're playing it safe.
powerpc/47x: defconfig for 476 on the iss 4xx simulator
From: Dave Kleikamp sha...@linux.vnet.ibm.com
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/configs/44x/iss476-smp_defconfig | 1023 +
1 files changed, 1023 insertions(+), 0 deletions(-)
powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores
From: Benjamin Herrenschmidt b...@kernel.crashing.org
There are still some unstable bits on the DD1 and DD1.1 cores. Don't use
the FPU or the tlbivax operation. Define CPU_FTR_476_DD1 and
CPU_FTR_476_DD1_1 for additional
powerpc/476: Add isync to the top of all exception handlers for DD1.1 core
From: Dave Kleikamp sha...@linux.vnet.ibm.com
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/asm-compat.h |7 ++-
arch/powerpc/kernel/head_booke.h |3 ++-
2 files
powerpc/476: Workaround for dcbf/dcbz workaround on DD1
From: Benjamin Herrenschmidt b...@kernel.crashing.org
On the DD1.1 core, the dcbf and dcbz instructions need to be preceded and
followed by an lwsync. We must trap user-space to ensure that this occurs
there too.
Signed-off-by: Benjamin
powerpc/476: Workaround for DD1.1: Issue lwsync after mtpid
From: Dave Kleikamp sha...@linux.vnet.ibm.com
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/asm-compat.h |2 ++
arch/powerpc/kernel/head_44x.S|1 +
2 files changed, 3
powerpc/476: Software workaround to fix dcr read/write sequencing.
From: Dave Kleikamp sha...@linux.vnet.ibm.com
Copy the register containing the dcr address to a spr before mfdcrx or
mtdcrx instruction. SPRN_SPRG_WSCRATCH_CRIT seems safe enough to use
as a dummy register, as it is only
powerpc/476: Add dci instruction to async interrupt handlers on DD1 core
From: Dave Kleikamp sha...@linux.vnet.ibm.com
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/asm-compat.h |5 +
arch/powerpc/kernel/head_booke.h |3 +++
2 files
On Mon, 1 Mar 2010, Albert Herranz wrote:
Also, I can't help thinking that the corresponding *_map() and
*_unmap() routines are so similar, it ought to be possible to combine
them. The only difference is a check for a NULL DMA address, and it's
not clear to me why it is present. It's
Alan Stern wrote:
If urb-num_sgs 0 then urb has been s-g mapped. Although we don't
currently check for it, quite a few URBs have transfer_buffer_length ==
0 (a number of control requests are like this, for example) so they
don't need a mapping either.
Ok, I'll use urb-num_sgs 0 to check
On 02/16/2010 02:41 PM, Grant Likely wrote:
[cc'd linux-kernel, linux-ide and Jeff Garzik]
Hi Roman.
you should use ./scripts/get_maintainer.pl to make sure you're cc'ing
the right people when posting patches. You should repost so that Jeff
has a copy of the patch to pick up (and add my
Overall I'm just going to trust you that things aren't broken on 47x :)
A few minor comments below. Also, if Torez and Benh contributed to this code,
then their S-o-b lines should be included as well (same goes for any other
patch).
On Mon, Mar 01, 2010 at 12:13:15PM -0700, Dave Kleikamp wrote:
On Mon, Mar 01, 2010 at 02:13:52PM -0500, Dave Kleikamp wrote:
powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores
From: Benjamin Herrenschmidt b...@kernel.crashing.org
There are still some unstable bits on the DD1 and DD1.1 cores. Don't use
the FPU or the tlbivax operation.
On Mon, Mar 01, 2010 at 12:16:00PM -0700, Dave Kleikamp wrote:
diff --git a/arch/powerpc/platforms/44x/Kconfig
b/arch/powerpc/platforms/44x/Kconfig
index 1dfc1c1..915c295 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -162,6 +162,17 @@ config YOSEMITE
On Mon, 1 Mar 2010, Albert Herranz wrote:
Am I on the right path?
More or less. I would do it somewhat differently:
If URB_NO_TRANSFER_DMA_MAP is set then no map is needed.
Otherwise if num_sgs 0 then no map is needed.
Otherwise if HCD_NO_COHERENT_MEM is set then use
On Mon, Mar 01, 2010 at 05:13:23AM -0700, Dave Kleikamp wrote:
powerpc/476: add machine check handler for 47x core
From: Dave Kleikamp sha...@linux.vnet.ibm.com
The 47x core's MCSR varies from 44x, so it needs it's own machine check
handler.
--- a/arch/powerpc/kernel/traps.c
+++
[Re: [PATCH] 8250: add workaround for MPC8[356]xx UART break IRQ storm] On
26/02/2010 (Fri 14:23) Scott Wood wrote:
On Fri, Feb 26, 2010 at 01:42:39PM -0600, Kumar Gala wrote:
On Feb 26, 2010, at 1:25 PM, Paul Gortmaker wrote:
Sending a break on the SOC UARTs found in some
Alan Stern wrote:
On Mon, 1 Mar 2010, Albert Herranz wrote:
Am I on the right path?
More or less. I would do it somewhat differently:
If URB_NO_TRANSFER_DMA_MAP is set then no map is needed.
Otherwise if num_sgs 0 then no map is needed.
Otherwise if HCD_NO_COHERENT_MEM is
sounds very much like this issue:
http://linux.derkeiler.com/Mailing-Lists/Kernel/2010-02/msg09470.html
(interrupt storm on the second port which is hit with breaks).
It's not the uart driver problem per se, the below fixes it:
*** linux/drivers/serial/serial_core.c#1Wed Feb 24
On Mon, 2010-03-01 at 15:19 -0500, Josh Boyer wrote:
Overall I'm just going to trust you that things aren't broken on 47x :)
A few minor comments below. Also, if Torez and Benh contributed to this code,
then their S-o-b lines should be included as well (same goes for any other
patch).
On Mon, 2010-03-01 at 15:08 -0600, Olof Johansson wrote:
On Mon, Mar 01, 2010 at 05:13:23AM -0700, Dave Kleikamp wrote:
powerpc/476: add machine check handler for 47x core
From: Dave Kleikamp sha...@linux.vnet.ibm.com
The 47x core's MCSR varies from 44x, so it needs it's own machine
On Mon, 2010-03-01 at 15:29 -0500, Josh Boyer wrote:
On Mon, Mar 01, 2010 at 12:16:00PM -0700, Dave Kleikamp wrote:
diff --git a/arch/powerpc/platforms/44x/Kconfig
b/arch/powerpc/platforms/44x/Kconfig
index 1dfc1c1..915c295 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++
On Mon, 2010-03-01 at 15:24 -0500, Josh Boyer wrote:
On Mon, Mar 01, 2010 at 02:13:52PM -0500, Dave Kleikamp wrote:
powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores
From: Benjamin Herrenschmidt b...@kernel.crashing.org
There are still some unstable bits on the DD1 and
Hi Albrecht,
On Mon, Mar 01, 2010 at 07:11:54PM +0100, Albrecht Dreß wrote:
On the MPC5200B, select the baud rate prescaler as /4 by default to make very
high baud rates (e.g. 3 MBaud) accessible and to achieve a higher precision
for high baud rates in general. For baud rates below ~500 Baud,
On Mon, Mar 01, 2010 at 05:11:29PM -0600, Dave Kleikamp wrote:
On Mon, 2010-03-01 at 15:19 -0500, Josh Boyer wrote:
Overall I'm just going to trust you that things aren't broken on 47x :)
A few minor comments below. Also, if Torez and Benh contributed to this
code,
then their S-o-b lines
2010/2/27 Peter Pan pppeterpp...@gmail.com:
2010/2/27 Scott Wood scottw...@freescale.com:
On Fri, Feb 26, 2010 at 10:08:09AM +0800, Peter Pan wrote:
There isn't one. I was not under the impression that such a configuration
was even possible (how do you control ALE/CLE, for example?). There
Problem solved. The NULL oops is due to the mtd-dev.class-p is NULL,
which makes the spin_lock in get_device_parent function uses a false
spin_lock_t struct.
the line is spin_lock(dev-class-p-class_dirs.list_lock);
That is mainly because in function add_mtd_device function uses the
static struct
Anatolij Gustschin wrote:
Hi Dan,
any chance this patch could be merged for 2.6.34 ?
Looks good to me, I'll include it in the dmaengine pull request.
--
Dan
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