Re: problem PCIe LSI detected at 32 device addresses (ppc460ex)
Ok, I've narrowed the scope of the problem some. I moved forward to a more recent kernel (2.6.31 to 2.6.36) and that resolved the problem of the controller showing up as every device on the bus. However, from 2.6.37 to the current HEAD, I have not been able to build a kernel to run on the 460EX. I tried 2.6.37, 2.6.38, and the HEAD and all result in the following kernel panic. I am not sure how to proceed here. I suppose we can stick with 2.6.36 since it works, but I'd like to understand what it might take to remedy this. Smells like somebody changed something with the OF flash code... Josh, Grant, any idea what's up there ? Cheers, Ben. Thanks U-Boot 2008.10 (Mar 15 2011 - 18:44:08) CPU: AMCC PowerPC 460EX Rev. A at 800 MHz (PLB=200, OPB=100, EBC=100 MHz) Security/Kasumi support Bootstrap Option D - Boot ROM Location PCI Internal PCI arbiter disabled 32 kB I-Cache 32 kB D-Cache Board: tanosx-slave - Tanisys SX Platform, 2*PCIeToggling PLX reset , Rev. 0 I2C: ready DRAM: Auto calibration |*** -- *** best_result window size: 231 *** best_result WRDTR: 0x0001 *** best_result CLKTR: 0x0001 *** best_result RQFD: 0x002e *** best_result RFFD: 0x0230 *** best_result RDCC: 0x4000 *** -- 512 MB (ECC enabled, 400 MHz, CL3) *** Warning - bad CRC, using default environment PCIE0: successfully set as endpoint PCIE1: successfully set as root-complex ### Unknown PB ### Net: No ethernet found. Type run flash_nfs to mount root filesystem over NFS Hit any key to stop autoboot: 0 ## Booting kernel from Legacy Image at ff00 ... Image Name: Linux-2.6.37-0-v2.6.37 Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size:2146637 Bytes = 2 MB Load Address: Entry Point: Verifying Checksum ... OK ## Loading init Ramdisk from Legacy Image at ff40 ... Image Name: Tanisys Ramdisk Image Image Type: PowerPC Linux RAMDisk Image (gzip compressed) Data Size:3830562 Bytes = 3.7 MB Load Address: Entry Point: Verifying Checksum ... OK ## Flattened Device Tree blob at ff3e Booting using the fdt blob at 0xff3e Uncompressing Kernel Image ... OK Loading Device Tree to 007fa000, end 007ffe96 ... OK Loading Ramdisk to 1fabe000, end 1fe65322 ... OK Using PowerPC 44x Platform machine description Linux version 2.6.37-0-v2.6.37 (aymane@lablinux) (gcc version 4.2.2) #16 Fri Apr 1 15:20:03 CDT 2011 Found initrd at 0xdfabe000:0xdfe65322 Zone PFN ranges: DMA 0x - 0x0002 Normal empty HighMem empty Movable zone start PFN for each node early_node_map[1] active PFN ranges 0: 0x - 0x0002 MMU: Allocated 1088 bytes of context maps for 255 contexts Built 1 zonelists in Zone order, mobility grouping on. Total pages: 130048 Kernel command line: root=/dev/ram rw mem=512M ip=tanosx-slave:eth0:off panic=1 console=ttyS0,5 7600 PID hash table entries: 2048 (order: 1, 8192 bytes) Dentry cache hash table entries: 65536 (order: 6, 262144 bytes) Inode-cache hash table entries: 32768 (order: 5, 131072 bytes) Memory: 510452k/524288k available (4180k kernel code, 13836k reserved, 160k data, 1144k bss, 180k i nit) Kernel virtual memory layout: * 0xfffcf000..0xf000 : fixmap * 0xffc0..0xffe0 : highmem PTEs * 0xff20..0xffc0 : consistent mem * 0xff20..0xff20 : early ioremap * 0xe100..0xff20 : vmalloc ioremap SLUB: Genslabs=13, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 NR_IRQS:512 UIC0 (32 IRQ sources) at DCR 0xc0 UIC1 (32 IRQ sources) at DCR 0xd0 UIC2 (32 IRQ sources) at DCR 0xe0 UIC3 (32 IRQ sources) at DCR 0xf0 clocksource: timebase mult[50] shift[22] registered pid_max: default: 4096 minimum: 301 Mount-cache hash table entries: 512 xor: measuring software checksum speed 8regs : 691.000 MB/sec 8regs_prefetch: 607.000 MB/sec 32regs: 882.000 MB/sec 32regs_prefetch: 748.000 MB/sec xor: using function: 32regs (882.000 MB/sec) NET: Registered protocol family 16 256k L2-cache enabled PCIE0: Checking link... PCIE0: Device detected, waiting for link... PCIE0: link is up ! PCI host bridge /plb/pciex@d (primary) ranges: MEM 0x000e..0x000e7fff - 0x8000 IO 0x000f8000..0x000f8000 - 0x 4xx PCI DMA offset set to 0x PCIE0: successfully set as endpoint PCIE1: Checking link... PCIE1: Device detected, waiting for link... PCIE1: link is up ! PCI host bridge /plb/pciex@d2000 (primary) ranges: MEM 0x000e8000..0x000e - 0x8000 IO 0x000f8001..0x000f8001 - 0x 4xx PCI DMA offset set to 0x PCIE1: successfully set as root-complex PCI host bridge /plb/pci@c0ec0 (primary)
Re: problem PCIe LSI detected at 32 device addresses (ppc460ex)
On Sun, Apr 3, 2011 at 3:52 PM, Benjamin Herrenschmidt b...@kernel.crashing.org wrote: Ok, I've narrowed the scope of the problem some. I moved forward to a more recent kernel (2.6.31 to 2.6.36) and that resolved the problem of the controller showing up as every device on the bus. However, from 2.6.37 to the current HEAD, I have not been able to build a kernel to run on the 460EX. I tried 2.6.37, 2.6.38, and the HEAD and all result in the following kernel panic. I am not sure how to proceed here. I suppose we can stick with 2.6.36 since it works, but I'd like to understand what it might take to remedy this. Smells like somebody changed something with the OF flash code... Josh, Grant, any idea what's up there ? Not sure, more information would be helpful. Ayman, if you do a 'git log v2.6.36.. drivers/mtd/maps/physmap_of.c', then you'll see a list of commits touching the mtd driver. Would you be able to do a 'git checkout sha1-id' on each of those are report back on at what point things stop working? Actually, a full bisect between 2.6.36 and 2.6.37 would be best, but this is a good start if you're limited on time. Once you find the first commit where it fails, do a 'git checkout sha1~1' to confirm that it is in fact the commit that causes the breakage. Can you also post your device tree please? Thanks, g. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v13 00/10] Add-Synopsys-DesignWare-HS-USB-OTG-driver
From: Tirumala Marri tma...@apm.com v13: 1. Remove redundant CONFIG VARIABLE from drivers/usb/dwc/Kconfig. v12: 1. dwc directory moved from otg to usb directory. Tirumala Marri (10): USB/ppc4xx: Add Synopsys DWC OTG Register definitions USB/ppc4xx: Add Synopsys DWC OTG driver framework USB/ppc4xx: Add Synopsys DWC OTG Core Interface Layer (CIL) USB/ppc4xx: Add Synopsys DWC OTG HCD function USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function USB/ppc4xx: Add Synopsys DWC OTG HCD queue function USB/ppc4xx: Add Synopsys DWC OTG PCD function USB ppc4xx: Add Synopsys DWC OTG PCD interrupt function USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile USB/ppc4xx:Synopsys DWC OTG driver enable gadget support drivers/Makefile |1 + drivers/usb/Kconfig |2 + drivers/usb/dwc/Kconfig | 84 ++ drivers/usb/dwc/Makefile | 19 + drivers/usb/dwc/apmppc.c | 414 +++ drivers/usb/dwc/cil.c | 972 +++ drivers/usb/dwc/cil.h | 1177 ++ drivers/usb/dwc/cil_intr.c| 616 + drivers/usb/dwc/driver.h | 76 ++ drivers/usb/dwc/hcd.c | 2465 + drivers/usb/dwc/hcd.h | 416 +++ drivers/usb/dwc/hcd_intr.c| 1477 ++ drivers/usb/dwc/hcd_queue.c | 696 +++ drivers/usb/dwc/param.c | 180 +++ drivers/usb/dwc/pcd.c | 1766 ++ drivers/usb/dwc/pcd.h | 139 +++ drivers/usb/dwc/pcd_intr.c| 2311 ++ drivers/usb/dwc/regs.h| 1326 drivers/usb/gadget/Kconfig| 11 + drivers/usb/gadget/gadget_chips.h |9 + 20 files changed, 14157 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/dwc/Kconfig create mode 100644 drivers/usb/dwc/Makefile create mode 100644 drivers/usb/dwc/apmppc.c create mode 100644 drivers/usb/dwc/cil.c create mode 100644 drivers/usb/dwc/cil.h create mode 100644 drivers/usb/dwc/cil_intr.c create mode 100644 drivers/usb/dwc/driver.h create mode 100644 drivers/usb/dwc/hcd.c create mode 100644 drivers/usb/dwc/hcd.h create mode 100644 drivers/usb/dwc/hcd_intr.c create mode 100644 drivers/usb/dwc/hcd_queue.c create mode 100644 drivers/usb/dwc/param.c create mode 100644 drivers/usb/dwc/pcd.c create mode 100644 drivers/usb/dwc/pcd.h create mode 100644 drivers/usb/dwc/pcd_intr.c create mode 100644 drivers/usb/dwc/regs.h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v13 01/10] USB/ppc4xx: Add Synopsys DWC OTG Register definitions
From: Tirumala Marri tma...@apm.com Add Synopsys Design Ware core register definitions. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/dwc/regs.h | 1326 1 files changed, 1326 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/dwc/regs.h diff --git a/drivers/usb/dwc/regs.h b/drivers/usb/dwc/regs.h new file mode 100644 index 000..d3694f3 --- /dev/null +++ b/drivers/usb/dwc/regs.h @@ -0,0 +1,1326 @@ +/* + * DesignWare HS OTG controller driver + * Copyright (C) 2006 Synopsys, Inc. + * Portions Copyright (C) 2010 Applied Micro Circuits Corporation. + * + * This program is free software: you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see http://www.gnu.org/licenses + * or write to the Free Software Foundation, Inc., 51 Franklin Street, + * Suite 500, Boston, MA 02110-1335 USA. + * + * Based on Synopsys driver version 2.60a + * Modified by Mark Miesfeld mmiesf...@apm.com + * + * Revamped register difinitions by Tirumala R Marri(tma...@apm.com) + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES + * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DWC_OTG_REGS_H__ +#define __DWC_OTG_REGS_H__ + +#include linux/types.h +/*Bit fields in the Device EP Transfer Size Register is 11 bits */ +#undef DWC_LIMITED_XFER_SIZE +/* + * This file contains the Macro defintions for accessing the DWC_otg core + * registers. + * + * The application interfaces with the HS OTG core by reading from and + * writing to the Control and Status Register (CSR) space through the + * AHB Slave interface. These registers are 32 bits wide, and the + * addresses are 32-bit-block aligned. + * CSRs are classified as follows: + * - Core Global Registers + * - Device Mode Registers + * - Device Global Registers + * - Device Endpoint Specific Registers + * - Host Mode Registers + * - Host Global Registers + * - Host Port CSRs + * - Host Channel Specific Registers + * + * Only the Core Global registers can be accessed in both Device and + * Host modes. When the HS OTG core is operating in one mode, either + * Device or Host, the application must not access registers from the + * other mode. When the core switches from one mode to another, the + * registers in the new mode of operation must be reprogrammed as they + * would be after a power-on reset. + */ + +/* + * DWC_otg Core registers. The core_global_regs structure defines the + * size and relative field offsets for the Core Global registers. + */ +#defineDWC_GOTGCTL 0x000 +#defineDWC_GOTGINT 0x004 +#defineDWC_GAHBCFG 0x008 +#defineDWC_GUSBCFG 0x00C +#defineDWC_GRSTCTL 0x010 +#defineDWC_GINTSTS 0x014 +#defineDWC_GINTMSK 0x018 +#defineDWC_GRXSTSR 0x01C +#defineDWC_GRXSTSP 0x020 +#defineDWC_GRXFSIZ 0x024 +#defineDWC_GNPTXFSIZ 0x028 +#defineDWC_GNPTXSTS0x02C +#defineDWC_GI2CCTL 0x030 +#defineDWC_VDCTL 0x034 +#defineDWC_GGPIO 0x038 +#defineDWC_GUID0x03C +#defineDWC_GSNPSID 0x040 +#defineDWC_GHWCFG1 0x044 +#defineDWC_GHWCFG2 0x048 +#defineDWC_GHWCFG3 0x04c +#defineDWC_GHWCFG4 0x050 +#defineDWC_HPTXFSIZ0x100 +#defineDWC_DPTX_FSIZ_DIPTXF(x) (0x104 + x * 4) /* 15 = x 1 */ + +#define DWC_GLBINTRMASK0x0001 +#define DWC_DMAENABLE 0x0020 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
[PATCH v13 02/10] USB/ppc4xx: Add Synopsys DWC OTG driver framework
From: Tirumala Marri tma...@apm.com
Platform probing is in dwc_otg_apmppc.c.
Driver parameter and parameter checking are in dwc_otg_param.c.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/apmppc.c | 414 ++
drivers/usb/dwc/driver.h | 76 +
drivers/usb/dwc/param.c | 180
3 files changed, 670 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/apmppc.c
create mode 100644 drivers/usb/dwc/driver.h
create mode 100644 drivers/usb/dwc/param.c
diff --git a/drivers/usb/dwc/apmppc.c b/drivers/usb/dwc/apmppc.c
new file mode 100644
index 000..ffbe6dd
--- /dev/null
+++ b/drivers/usb/dwc/apmppc.c
@@ -0,0 +1,414 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * The dwc_otg module provides the initialization and cleanup entry
+ * points for the dwcotg driver. This module will be dynamically installed
+ * after Linux is booted using the insmod command. When the module is
+ * installed, the dwc_otg_driver_init function is called. When the module is
+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
+ *
+ * This module also defines a data structure for the dwc_otg driver, which is
+ * used in conjunction with the standard device structure. These
+ * structures allow the OTG driver to comply with the standard Linux driver
+ * model in which devices and drivers are registered with a bus driver. This
+ * has the benefit that Linux can expose attributes of the driver and device
+ * in its special sysfs file system. Users can then read or write files in
+ * this file system to perform diagnostics on the driver components or the
+ * device.
+ */
+
+#include linux/of_platform.h
+
+#include driver.h
+
+#define DWC_DRIVER_VERSION 1.05
+#define DWC_DRIVER_DESCHS OTG USB Controller driver
+static const char dwc_driver_name[] = dwc_otg;
+
+/**
+ * This function is the top level interrupt handler for the Common
+ * (Device and host modes) interrupts.
+ */
+static irqreturn_t dwc_otg_common_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+ int retval;
+
+ retval = dwc_otg_handle_common_intr(dwc_dev-core_if);
+ return IRQ_RETVAL(retval);
+}
+
+/**
+ * This function is the interrupt handler for the OverCurrent condition
+ * from the external charge pump (if enabled)
+ */
+static irqreturn_t dwc_otg_externalchgpump_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+
+ if (dwc_otg_is_host_mode(dwc_dev-core_if)) {
+ struct dwc_hcd *dwc_hcd;
+ u32 hprt0 = 0;
+
+ dwc_hcd = dwc_dev-hcd;
+ spin_lock(dwc_hcd-lock);
+ dwc_hcd-flags.b.port_over_current_change = 1;
+
+ hprt0 = DWC_HPRT0_PRT_PWR_RW(hprt0, 0);
+ dwc_write32(dwc_dev-core_if-host_if-hprt0, hprt0);
+ spin_unlock(dwc_hcd-lock);
+ } else {
+ /* Device mode - This int is n/a for device mode */
+ dev_dbg(dev, DeviceMode: OTG OverCurrent Detected\n);
+ }
+
+ return
[PATCH v13 05/10] USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function
From: Tirumala Marri tma...@apm.com
Implements DWC OTG USB HCD interrupt service routine.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/hcd_intr.c | 1477
1 files changed, 1477 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/hcd_intr.c
diff --git a/drivers/usb/dwc/hcd_intr.c b/drivers/usb/dwc/hcd_intr.c
new file mode 100644
index 000..26079a6
--- /dev/null
+++ b/drivers/usb/dwc/hcd_intr.c
@@ -0,0 +1,1477 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include hcd.h
+
+/* This file contains the implementation of the HCD Interrupt handlers.
*/
+static const int erratum_usb09_patched;
+static const int deferral_on = 1;
+static const int nak_deferral_delay = 8;
+static const int nyet_deferral_delay = 1;
+
+/**
+ * Handles the start-of-frame interrupt in host mode. Non-periodic
+ * transactions may be queued to the DWC_otg controller for the current
+ * (micro)frame. Periodic transactions may be queued to the controller for the
+ * next (micro)frame.
+ */
+static int dwc_otg_hcd_handle_sof_intr(struct dwc_hcd *hcd)
+{
+ u32 hfnum = 0;
+ struct list_head *qh_entry;
+ struct dwc_qh *qh;
+ enum dwc_transaction_type tr_type;
+ u32 gintsts = 0;
+
+ hfnum =
+ dwc_read32(hcd-core_if-host_if-host_global_regs +
+ DWC_HFNUM);
+
+ hcd-frame_number = DWC_HFNUM_FRNUM_RD(hfnum);
+
+ /* Determine whether any periodic QHs should be executed. */
+ qh_entry = hcd-periodic_sched_inactive.next;
+ while (qh_entry != hcd-periodic_sched_inactive) {
+ qh = list_entry(qh_entry, struct dwc_qh, qh_list_entry);
+ qh_entry = qh_entry-next;
+
+ /*
+* If needed, move QH to the ready list to be executed next
+* (micro)frame.
+*/
+ if (dwc_frame_num_le(qh-sched_frame, hcd-frame_number))
+ list_move(qh-qh_list_entry,
+ hcd-periodic_sched_ready);
+ }
+
+ tr_type = dwc_otg_hcd_select_transactions(hcd);
+ if (tr_type != DWC_OTG_TRANSACTION_NONE)
+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
+
+ /* Clear interrupt */
+ gintsts |= DWC_INTMSK_STRT_OF_FRM;
+ dwc_write32(gintsts_reg(hcd), gintsts);
+ return 1;
+}
+
+/**
+ * Handles the Rx Status Queue Level Interrupt, which indicates that there is
at
+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
+ * memory if the DWC_otg controller is operating in Slave mode.
+ */
+static int dwc_otg_hcd_handle_rx_status_q_level_intr(struct dwc_hcd *hcd)
+{
+ u32 grxsts;
+ struct dwc_hc *hc;
+
+ grxsts = dwc_read32(hcd-core_if-core_global_regs + DWC_GRXSTSP);
+ hc = hcd-hc_ptr_array[grxsts DWC_HM_RXSTS_CHAN_NUM_RD(grxsts)];
+
+ /* Packet Status */
+ switch (DWC_HM_RXSTS_PKT_STS_RD(grxsts)) {
+ case DWC_GRXSTS_PKTSTS_IN:
+ /* Read the data into the host buffer. */
+
[PATCH v13 06/10] USB/ppc4xx: Add Synopsys DWC OTG HCD queue function
From: Tirumala Marri tma...@apm.com
Implements functions to manage Queue Heads and Queue
Transfer Descriptors of DWC USB OTG Controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/hcd_queue.c | 696 +++
1 files changed, 696 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/hcd_queue.c
diff --git a/drivers/usb/dwc/hcd_queue.c b/drivers/usb/dwc/hcd_queue.c
new file mode 100644
index 000..1f99573
--- /dev/null
+++ b/drivers/usb/dwc/hcd_queue.c
@@ -0,0 +1,696 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file contains the functions to manage Queue Heads and Queue
+ * Transfer Descriptors.
+ */
+
+#include hcd.h
+
+static inline int is_fs_ls(enum usb_device_speed speed)
+{
+ return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
+}
+
+/* Allocates memory for a QH structure. */
+static inline struct dwc_qh *dwc_otg_hcd_qh_alloc(void)
+{
+ return kmalloc(sizeof(struct dwc_qh), GFP_ATOMIC);
+}
+
+/**
+ * Initializes a QH structure to initialize the QH.
+ */
+#define SCHEDULE_SLOP 10
+static void dwc_otg_hcd_qh_init(struct dwc_hcd *hcd, struct dwc_qh *qh,
+ struct urb *urb)
+{
+ memset(qh, 0, sizeof(struct dwc_qh));
+
+ /* Initialize QH */
+ switch (usb_pipetype(urb-pipe)) {
+ case PIPE_CONTROL:
+ qh-ep_type = USB_ENDPOINT_XFER_CONTROL;
+ break;
+ case PIPE_BULK:
+ qh-ep_type = USB_ENDPOINT_XFER_BULK;
+ break;
+ case PIPE_ISOCHRONOUS:
+ qh-ep_type = USB_ENDPOINT_XFER_ISOC;
+ break;
+ case PIPE_INTERRUPT:
+ qh-ep_type = USB_ENDPOINT_XFER_INT;
+ break;
+ }
+
+ qh-ep_is_in = usb_pipein(urb-pipe) ? 1 : 0;
+ qh-data_toggle = DWC_OTG_HC_PID_DATA0;
+ qh-maxp = usb_maxpacket(urb-dev, urb-pipe, !(usb_pipein(urb-pipe)));
+
+ INIT_LIST_HEAD(qh-qtd_list);
+ INIT_LIST_HEAD(qh-qh_list_entry);
+
+ qh-channel = NULL;
+ qh-speed = urb-dev-speed;
+
+ /*
+* FS/LS Enpoint on HS Hub NOT virtual root hub
+*/
+ qh-do_split = 0;
+ if (is_fs_ls(urb-dev-speed) urb-dev-tt urb-dev-tt-hub
+ urb-dev-tt-hub-devnum != 1)
+ qh-do_split = 1;
+
+ if (qh-ep_type == USB_ENDPOINT_XFER_INT ||
+ qh-ep_type == USB_ENDPOINT_XFER_ISOC) {
+ /* Compute scheduling parameters once and save them. */
+ u32 hprt;
+ int bytecount = dwc_hb_mult(qh-maxp) *
+ dwc_max_packet(qh-maxp);
+
+ qh-usecs = NS_TO_US(usb_calc_bus_time(urb-dev-speed,
+ usb_pipein(urb-pipe),
+ (qh-ep_type ==
+ USB_ENDPOINT_XFER_ISOC),
+ bytecount));
+
+ /* Start in a slightly future (micro)frame. */
+
[PATCH v13 07/10] USB/ppc4xx: Add Synopsys DWC OTG PCD function
From: Tirumala Marri tma...@apm.com
The PCD is responsible for translating requests from the gadget driver
to appropriate actions on the DWC OTG controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/pcd.c | 1766 +
drivers/usb/dwc/pcd.h | 139
2 files changed, 1905 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/pcd.c
create mode 100644 drivers/usb/dwc/pcd.h
diff --git a/drivers/usb/dwc/pcd.c b/drivers/usb/dwc/pcd.c
new file mode 100644
index 000..04a0a4a
--- /dev/null
+++ b/drivers/usb/dwc/pcd.c
@@ -0,0 +1,1766 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file implements the Peripheral Controller Driver.
+ *
+ * The Peripheral Controller Driver (PCD) is responsible for
+ * translating requests from the Function Driver into the appropriate
+ * actions on the DWC_otg controller. It isolates the Function Driver
+ * from the specifics of the controller by providing an API to the
+ * Function Driver.
+ *
+ * The Peripheral Controller Driver for Linux will implement the
+ * Gadget API, so that the existing Gadget drivers can be used.
+ * (Gadget Driver is the Linux terminology for a Function Driver.)
+ *
+ * The Linux Gadget API is defined in the header file linux/usb/gadget.h. The
+ * USB EP operations API is defined in the structure usb_ep_ops and the USB
+ * Controller API is defined in the structure usb_gadget_ops
+ *
+ * An important function of the PCD is managing interrupts generated
+ * by the DWC_otg controller. The implementation of the DWC_otg device
+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
+ */
+
+#include linux/dma-mapping.h
+#include linux/delay.h
+
+#include pcd.h
+
+/*
+ * Static PCD pointer for use in usb_gadget_register_driver and
+ * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
+ */
+static struct dwc_pcd *s_pcd;
+
+static inline int need_stop_srp_timer(struct core_if *core_if)
+{
+ if (core_if-core_params-phy_type != DWC_PHY_TYPE_PARAM_FS ||
+ !core_if-core_params-i2c_enable)
+ return core_if-srp_timer_started ? 1 : 0;
+ return 0;
+}
+
+/**
+ * Tests if the module is set to FS or if the PHY_TYPE is FS. If so, then the
+ * gadget should not report as dual-speed capable.
+ */
+static inline int check_is_dual_speed(struct core_if *core_if)
+{
+ if (core_if-core_params-speed == DWC_SPEED_PARAM_FULL ||
+ (DWC_HWCFG2_HS_PHY_TYPE_RD(core_if-hwcfg2) == 2
+DWC_HWCFG2_P_2_P_RD(core_if-hwcfg2) == 1
+core_if-core_params-ulpi_fs_ls))
+ return 0;
+ return 1;
+}
+
+/**
+ * Tests if driver is OTG capable.
+ */
+static inline int check_is_otg(struct core_if *core_if)
+{
+ if (DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2)
[PATCH v13 09/10] USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile
From: Tirumala Marri tma...@apm.com Add Synopsys DesignWare HS USB OTG driver kernel configuration. Synopsys OTG driver may operate in host only, device only, or OTG mode. The driver also allows user configure the core to use its internal DMA or Slave (PIO) mode. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/Makefile |1 + drivers/usb/Kconfig |2 + drivers/usb/dwc/Kconfig | 84 ++ drivers/usb/dwc/Makefile | 19 ++ 4 files changed, 106 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/dwc/Kconfig create mode 100644 drivers/usb/dwc/Makefile diff --git a/drivers/Makefile b/drivers/Makefile index a125e0b..d4133a6 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_PARIDE) += block/paride/ obj-$(CONFIG_TC) += tc/ obj-$(CONFIG_UWB) += uwb/ obj-$(CONFIG_USB_OTG_UTILS)+= usb/otg/ +obj-$(CONFIG_USB_DWC_OTG) += usb/dwc/ obj-$(CONFIG_USB) += usb/ obj-$(CONFIG_USB_MUSB_HDRC)+= usb/musb/ obj-$(CONFIG_PCI) += usb/ diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 41b6e51..1daed15 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -115,6 +115,8 @@ source drivers/usb/host/Kconfig source drivers/usb/musb/Kconfig +source drivers/usb/dwc/Kconfig + source drivers/usb/class/Kconfig source drivers/usb/storage/Kconfig diff --git a/drivers/usb/dwc/Kconfig b/drivers/usb/dwc/Kconfig new file mode 100644 index 000..eafc5ed --- /dev/null +++ b/drivers/usb/dwc/Kconfig @@ -0,0 +1,84 @@ +# +# USB Dual Role (OTG-ready) Controller Drivers +# for silicon based on Synopsys DesignWare IP +# + +comment Enable Host or Gadget support for DesignWare OTG controller + depends on !USB USB_GADGET=n + +config USB_DWC_OTG + tristate Synopsys DWC OTG Controller + depends on USB || USB_GADGET + select NOP_USB_XCEIV + select USB_OTG_UTILS + default USB_GADGET + help + This driver provides USB Device Controller support for the + Synopsys DesignWare USB OTG Core used on the AppliedMicro PowerPC SoC. + +config DWC_DEBUG + bool Enable DWC Debugging + depends on USB_DWC_OTG + default n + help + Enable DWC driver debugging + +choice + prompt DWC Mode Selection + depends on USB_DWC_OTG + default DWC_HOST_ONLY + help + Select the DWC Core in OTG, Host only, or Device only mode. + +config DWC_HOST_ONLY + bool DWC Host Only Mode + +config DWC_OTG_MODE + bool DWC OTG Mode + select USB_GADGET_SELECTED + +config DWC_DEVICE_ONLY + bool DWC Device Only Mode + select USB_GADGET_SELECTED + +endchoice + +# enable peripheral support (including with OTG) +choice + prompt DWC DMA/SlaveMode Selection + depends on USB_DWC_OTG + default DWC_DMA_MODE + help + Select the DWC DMA or Slave Mode. + DMA mode uses the DWC core internal DMA engines. + Slave mode uses the processor PIO to tranfer data. + In Slave mode, processor's DMA channels can be used if available. + +config DWC_SLAVE + bool DWC Slave Mode + +config DWC_DMA_MODE + bool DWC DMA Mode + +endchoice + +config DWC_OTG_REG_LE + bool DWC Little Endian Register + depends on USB_DWC_OTG + default y + help + OTG core register access is Little-Endian. + +config DWC_OTG_FIFO_LE + bool DWC FIFO Little Endian + depends on USB_DWC_OTG + default n + help + OTG core FIFO access is Little-Endian. + +config DWC_LIMITED_XFER_SIZE + bool DWC Endpoint Limited Xfer Size + depends on USB_GADGET_DWC_HDRC + default n + help + Bit fields in the Device EP Transfer Size Register is 11 bits. diff --git a/drivers/usb/dwc/Makefile b/drivers/usb/dwc/Makefile new file mode 100644 index 000..4102add --- /dev/null +++ b/drivers/usb/dwc/Makefile @@ -0,0 +1,19 @@ +# +# OTG infrastructure and transceiver drivers +# +obj-$(CONFIG_USB_DWC_OTG) += dwc.o + +dwc-objs := cil.o cil_intr.o param.o + +ifeq ($(CONFIG_4xx_SOC),y) +dwc-objs += apmppc.o +endif + +ifneq ($(CONFIG_DWC_DEVICE_ONLY),y) +dwc-objs += hcd.o hcd_intr.o \ + hcd_queue.o +endif + +ifneq ($(CONFIG_DWC_HOST_ONLY),y) +dwc-objs += pcd.o pcd_intr.o +endif -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v13 10/10] USB/ppc4xx:Synopsys DWC OTG driver enable gadget support
From: Tirumala Marri tma...@apm.com Enable gadget support Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/gadget/Kconfig| 11 +++ drivers/usb/gadget/gadget_chips.h |9 + 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index bc5123c..b641c0a 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -365,6 +365,17 @@ config USB_GADGET_MUSB_HDRC This OTG-capable silicon IP is used in dual designs including the TI DaVinci, OMAP 243x, OMAP 343x, TUSB 6010, and ADI Blackfin +# dwc_otg builds in ../dwc along with host support +config USB_GADGET_DWC_HDRC + boolean DesignWare USB Peripheral + depends on DWC_OTG_MODE || DWC_DEVICE_ONLY + select USB_GADGET_DUALSPEED + select USB_GADGET_SELECTED + select USB_GADGET_DWC_OTG + help + This OTG-capable Designware USB IP which has host and device + modes. + config USB_GADGET_M66592 boolean Renesas M66592 USB Peripheral Controller select USB_GADGET_DUALSPEED diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index e896f63..d1fab43 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -136,6 +136,12 @@ #define gadget_is_s3c_hsotg(g)0 #endif +#if defined(CONFIG_DWC_OTG_MODE) || defined(CONFIG_DWC_DEVICE_ONLY) +#define gadget_is_dwc_otg_pcd(g) (!strcmp(dwc_otg_pcd, (g)-name)) +#else +#define gadget_is_dwc_otg_pcd(g) 0 +#endif + #ifdef CONFIG_USB_GADGET_EG20T #definegadget_is_pch(g)(!strcmp(pch_udc, (g)-name)) #else @@ -207,6 +213,9 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x27; else if (gadget_is_ci13xxx_msm(gadget)) return 0x28; + else if (gadget_is_dwc_otg_pcd(gadget)) + return 0x29; + return -ENOENT; } -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: problem PCIe LSI detected at 32 device addresses (ppc460ex)
On Sun, Apr 03, 2011 at 04:09:26PM -0600, Grant Likely wrote:
On Sun, Apr 3, 2011 at 3:52 PM, Benjamin Herrenschmidt
b...@kernel.crashing.org wrote:
Ok, I've narrowed the scope of the problem some. ?I moved forward
to a more recent kernel (2.6.31 to 2.6.36) and that resolved the
problem of the controller showing up as every device on the bus.
However, from 2.6.37 to the current HEAD, I have not been able to
build a kernel to run on the 460EX. ?I tried 2.6.37, 2.6.38, and
the HEAD and all result in the following kernel panic. ?I am not
sure how to proceed here. ?I suppose we can stick with 2.6.36 since
it works, but I'd like to understand what it might take to remedy
this.
Smells like somebody changed something with the OF flash code... Josh,
Grant, any idea what's up there ?
Not sure, more information would be helpful.
Ayman, if you do a 'git log v2.6.36.. drivers/mtd/maps/physmap_of.c',
then you'll see a list of commits touching the mtd driver. Would you
be able to do a 'git checkout sha1-id' on each of those are report
back on at what point things stop working? Actually, a full bisect
between 2.6.36 and 2.6.37 would be best, but this is a good start if
you're limited on time. Once you find the first commit where it
fails, do a 'git checkout sha1~1' to confirm that it is in fact the
commit that causes the breakage.
I can try to find the commit tomorrow. In the interim, i've pasted
the dts below. The board was originally based on the canyonlands, but
we've made some changes, mostly to the pcie. we run the 1-l port in
endpoint mode, we have a chain of plx switches and devices on the 4-l
port. One item that I don't think would matter, but is not too common
is that we are booting these over the pci bus from another PPCs memory.
I only mention this since this failure is during boot, though everything
should by local to the cpu by this time.
Can you also post your device tree please?
Here is the device tree for our custom board.
/dts-v1/;
/ {
#address-cells = 2;
#size-cells = 1;
model = amcc,canyonlands;
compatible = amcc,canyonlands;
dcr-parent = {/cpus/cpu@0};
aliases {
ethernet0 = EMAC0;
ethernet1 = EMAC1;
serial0 = UART0;
serial1 = UART1;
};
cpus {
#address-cells = 1;
#size-cells = 0;
cpu@0 {
device_type = cpu;
model = PowerPC,460EX;
reg = 0x;
clock-frequency = 0; /* Filled in by U-Boot */
timebase-frequency = 0; /* Filled in by U-Boot */
i-cache-line-size = 32;
d-cache-line-size = 32;
i-cache-size = 32768;
d-cache-size = 32768;
dcr-controller;
dcr-access-method = native;
};
};
memory {
device_type = memory;
reg = 0x 0x 0x; /* Filled in by
U-Boot */
};
UIC0: interrupt-controller0 {
compatible = ibm,uic-460ex,ibm,uic;
interrupt-controller;
cell-index = 0;
dcr-reg = 0x0c0 0x009;
#address-cells = 0;
#size-cells = 0;
#interrupt-cells = 2;
};
UIC1: interrupt-controller1 {
compatible = ibm,uic-460ex,ibm,uic;
interrupt-controller;
cell-index = 1;
dcr-reg = 0x0d0 0x009;
#address-cells = 0;
#size-cells = 0;
#interrupt-cells = 2;
interrupts = 0x1e 0x4 0x1f 0x4; /* cascade */
interrupt-parent = UIC0;
};
UIC2: interrupt-controller2 {
compatible = ibm,uic-460ex,ibm,uic;
interrupt-controller;
cell-index = 2;
dcr-reg = 0x0e0 0x009;
#address-cells = 0;
#size-cells = 0;
#interrupt-cells = 2;
interrupts = 0xa 0x4 0xb 0x4; /* cascade */
interrupt-parent = UIC0;
};
UIC3: interrupt-controller3 {
compatible = ibm,uic-460ex,ibm,uic;
interrupt-controller;
cell-index = 3;
dcr-reg = 0x0f0 0x009;
#address-cells = 0;
#size-cells = 0;
#interrupt-cells = 2;
interrupts = 0x10 0x4 0x11 0x4; /* cascade */
interrupt-parent = UIC0;
};
SDR0: sdr {
compatible = ibm,sdr-460ex;
dcr-reg = 0x00e 0x002;
};
CPR0: cpr {
compatible = ibm,cpr-460ex;
dcr-reg = 0x00c
[RFC/PATCH] of: Match PCI devices to OF nodes generically
powerpc has two different ways of matching PCI devices to their
corresponding OF node (if any) for historical reasons. The ppc64 one
does a scan looking for matching bus/dev/fn, while the ppc32 one does a
scan looking only for matching dev/fn on each level in order to be
agnostic to busses being renumbered (which Linux does on some
platforms).
This removes both and instead moves the matching code to the PCI core
itself. It's the most logical place to do it: when a pci_dev is created,
we know the parent and thus can do a single level scan for the matching
device_node (if any).
The benefit is that all archs now get the matching for free. There's one
hook the arch might want to provide to match a PHB bus to its device
node. A default weak implementation is provided that looks for the
parent device device node, but it's not entirely reliable on powerpc for
various reasons so powerpc provides its own.
Dave, I don't think I broke anything in sparc land but I haven't tested
(and have to admit haven't build-tested yet either).
Not-signed-off-yet. Tested on a few ppc's but not the whole range yet
either, mostly posted for comments.
arch/powerpc/include/asm/pci-bridge.h | 31 +-
arch/powerpc/include/asm/pci.h|3 --
arch/powerpc/include/asm/prom.h |1
arch/powerpc/kernel/pci-common.c | 11 +--
arch/powerpc/kernel/pci_32.c |6
arch/powerpc/kernel/pci_dn.c | 47
--
arch/powerpc/kernel/pci_of_scan.c |9 ++
arch/sparc/kernel/pci.c |2 -
drivers/pci/Makefile |2 +
drivers/pci/hotplug/rpadlpar_core.c |2 -
drivers/pci/probe.c |8 +
include/linux/pci.h | 17
12 files changed, 46 insertions(+), 93 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h
index 5e156e0..a4c8e4a 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -169,18 +169,18 @@ static inline struct pci_controller
*pci_bus_to_host(const struct pci_bus *bus)
return bus-sysdata;
}
-#ifndef CONFIG_PPC64
+static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
+{
+ return dev-dev.of_node;
+}
static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
{
- struct pci_controller *host;
-
- if (bus-self)
- return pci_device_to_OF_node(bus-self);
- host = pci_bus_to_host(bus);
- return host ? host-dn : NULL;
+ return bus-dev.of_node;
}
+#ifndef CONFIG_PPC64
+
static inline int isa_vaddr_is_ioport(void __iomem *address)
{
/* No specific ISA handling on ppc32 at this stage, it
@@ -223,17 +223,8 @@ struct pci_dn {
/* Get the pointer to a device_node's pci_dn */
#define PCI_DN(dn) ((struct pci_dn *) (dn)-data)
-extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
extern void * update_dn_pci_info(struct device_node *dn, void *data);
-/* Get a device_node from a pci_dev. This code must be fast except
- * in the case where the sysdata is incorrect and needs to be fixed
- * up (this will only happen once). */
-static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
-{
- return dev-dev.of_node ? dev-dev.of_node : fetch_dev_dn(dev);
-}
-
static inline int pci_device_from_OF_node(struct device_node *np,
u8 *bus, u8 *devfn)
{
@@ -244,14 +235,6 @@ static inline int pci_device_from_OF_node(struct
device_node *np,
return 0;
}
-static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
-{
- if (bus-self)
- return pci_device_to_OF_node(bus-self);
- else
- return bus-dev.of_node; /* Must be root bus (PHB) */
-}
-
/** Find the bus corresponding to the indicated device node */
extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
index 7d77909..1f52268 100644
--- a/arch/powerpc/include/asm/pci.h
+++ b/arch/powerpc/include/asm/pci.h
@@ -179,8 +179,7 @@ extern int remove_phb_dynamic(struct pci_controller *phb);
extern struct pci_dev *of_create_pci_dev(struct device_node *node,
struct pci_bus *bus, int devfn);
-extern void of_scan_pci_bridge(struct device_node *node,
- struct pci_dev *dev);
+extern void of_scan_pci_bridge(struct pci_dev *dev);
extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus);
diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
index c189aa5..2b888cc 100644
--- a/arch/powerpc/include/asm/prom.h
+++ b/arch/powerpc/include/asm/prom.h
@@ -32,7 +32,6 @@ struct pci_dev;
extern int
Re: [RFC/PATCH] of: Match PCI devices to OF nodes generically
On Mon, 2011-04-04 at 12:04 +1000, Benjamin Herrenschmidt wrote:
powerpc has two different ways of matching PCI devices to their
corresponding OF node (if any) for historical reasons. The ppc64 one
does a scan looking for matching bus/dev/fn, while the ppc32 one does a
scan looking only for matching dev/fn on each level in order to be
agnostic to busses being renumbered (which Linux does on some
platforms).
This removes both and instead moves the matching code to the PCI core
itself. It's the most logical place to do it: when a pci_dev is created,
we know the parent and thus can do a single level scan for the matching
device_node (if any).
The benefit is that all archs now get the matching for free. There's one
hook the arch might want to provide to match a PHB bus to its device
node. A default weak implementation is provided that looks for the
parent device device node, but it's not entirely reliable on powerpc for
various reasons so powerpc provides its own.
Dave, I don't think I broke anything in sparc land but I haven't tested
(and have to admit haven't build-tested yet either).
Not-signed-off-yet. Tested on a few ppc's but not the whole range yet
either, mostly posted for comments.
Nice, looks like I forgot to add the new drivers/pci/of.c file :-)
Here's a new patch. Also added linux-pci to the CC list.
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h
index 5e156e0..a4c8e4a 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -169,18 +169,18 @@ static inline struct pci_controller
*pci_bus_to_host(const struct pci_bus *bus)
return bus-sysdata;
}
-#ifndef CONFIG_PPC64
+static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
+{
+ return dev-dev.of_node;
+}
static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
{
- struct pci_controller *host;
-
- if (bus-self)
- return pci_device_to_OF_node(bus-self);
- host = pci_bus_to_host(bus);
- return host ? host-dn : NULL;
+ return bus-dev.of_node;
}
+#ifndef CONFIG_PPC64
+
static inline int isa_vaddr_is_ioport(void __iomem *address)
{
/* No specific ISA handling on ppc32 at this stage, it
@@ -223,17 +223,8 @@ struct pci_dn {
/* Get the pointer to a device_node's pci_dn */
#define PCI_DN(dn) ((struct pci_dn *) (dn)-data)
-extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
extern void * update_dn_pci_info(struct device_node *dn, void *data);
-/* Get a device_node from a pci_dev. This code must be fast except
- * in the case where the sysdata is incorrect and needs to be fixed
- * up (this will only happen once). */
-static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
-{
- return dev-dev.of_node ? dev-dev.of_node : fetch_dev_dn(dev);
-}
-
static inline int pci_device_from_OF_node(struct device_node *np,
u8 *bus, u8 *devfn)
{
@@ -244,14 +235,6 @@ static inline int pci_device_from_OF_node(struct
device_node *np,
return 0;
}
-static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
-{
- if (bus-self)
- return pci_device_to_OF_node(bus-self);
- else
- return bus-dev.of_node; /* Must be root bus (PHB) */
-}
-
/** Find the bus corresponding to the indicated device node */
extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
index 7d77909..1f52268 100644
--- a/arch/powerpc/include/asm/pci.h
+++ b/arch/powerpc/include/asm/pci.h
@@ -179,8 +179,7 @@ extern int remove_phb_dynamic(struct pci_controller *phb);
extern struct pci_dev *of_create_pci_dev(struct device_node *node,
struct pci_bus *bus, int devfn);
-extern void of_scan_pci_bridge(struct device_node *node,
- struct pci_dev *dev);
+extern void of_scan_pci_bridge(struct pci_dev *dev);
extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus);
diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
index c189aa5..2b888cc 100644
--- a/arch/powerpc/include/asm/prom.h
+++ b/arch/powerpc/include/asm/prom.h
@@ -32,7 +32,6 @@ struct pci_dev;
extern int pci_device_from_OF_node(struct device_node *node,
u8* bus, u8* devfn);
extern struct device_node* pci_busdev_to_OF_node(struct pci_bus *, int);
-extern struct device_node* pci_device_to_OF_node(struct pci_dev *);
extern void pci_create_OF_bus_map(void);
#endif
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 893af2a..47c516b 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -1097,9 +1097,6
