On 07/15/2013 11:36 AM, Aneesh Kumar K.V wrote:
Anshuman Khandual khand...@linux.vnet.ibm.com writes:
On 07/10/2013 06:32 PM, Mahesh J Salgaonkar wrote:
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
During Machine Check interrupt on pseries platform, R3 generally points to
memory
On Mon, 2013-07-15 at 14:04 +1000, Anton Blanchard wrote:
Module CRCs are implemented as absolute symbols that get resolved by
a linker script. We build an intermediate .o that contains an
unresolved symbol for each CRC. genksysms parses this .o, calculates
the CRCs and writes a linker script
On 07/14/2013 04:32 PM, Paul Bolle wrote:
The Kconfig symbol HOTPLUG was removed with commit 40b313608a (Finally
eradicate CONFIG_HOTPLUG). But there's still one select statement for
that symbol. It seems that select statement was added after the patch to
remove CONFIG_HOTPLUG was submitted.
+#define MFTB(dest, scratch1, scratch2) \
+90: mftbu scratch1; \
+ mftbl dest; \
+ mftbu scratch2; \
+ cmpwscratch1,scratch2; \
+ bne 90b;\
+ rldimi dest,scratch1,32,0;
Are the
Overview of P1020RDB-PD device:
- DDR3 2GB
- NOR flash 64MB
- NAND flash 128MB
- SPI flash 16MB
- I2C EEPROM 256Kb
- eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch
- eTSEC2 (SGMII PHY)
- eTSEC3 (RGMII PHY)
- SDHC
- 1 USB ports
- TDM ports
- PCIe
Signed-off-by: Haijun Zhang
Anyone, ping?
On 07/06/2013 02:16 PM, Alexey Kardashevskiy wrote:
This adds hash_for_each_possible_rcu_notrace() which is basically
a notrace clone of hash_for_each_possible_rcu() which cannot be
used in real mode due to its tracing/debugging capability.
Signed-off-by: Alexey Kardashevskiy
On Fri, May 31, 2013 at 05:09:51PM -0700, Dan Williams wrote:
On Thu, May 30, 2013 at 10:47 AM, Vinod Koul vinod.k...@intel.com wrote:
On Mon, May 27, 2013 at 03:14:30PM +0300, Andy Shevchenko wrote:
Here is a set of small independent patches that clean up or fix minor
things
across DMA
On Thu, May 30, 2013 at 09:32:19PM +0300, Andy Shevchenko wrote:
Here is a set of small independent patches that clean up or fix minor
things
across DMA slave drivers.
Applied thanks
--
~Vinod
___
Linuxppc-dev mailing list
On Mon, 2013-07-15 at 15:07 +0530, Vinod Koul wrote:
On Thu, May 30, 2013 at 09:32:19PM +0300, Andy Shevchenko wrote:
Here is a set of small independent patches that clean up or fix minor
things
across DMA slave drivers.
Applied thanks
Thank you. You were faster than me, I was just
From: Hongbo Zhang hongbo.zh...@freescale.com
This patch adds support to 8-channel DMA engine, thus the driver works for both
the new 8-channel and the legacy 4-channel DMA engines.
Signed-off-by: Hongbo Zhang hongbo.zh...@freescale.com
---
drivers/dma/Kconfig |9 +
From: Hongbo Zhang hongbo.zh...@freescale.com
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch add
the device tree nodes for them.
Signed-off-by: Hongbo Zhang hongbo.zh...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/dma.txt|8 +-
On Mon, Jul 15, 2013 at 01:21:17PM +0300, Andy Shevchenko wrote:
On Mon, 2013-07-15 at 15:07 +0530, Vinod Koul wrote:
On Thu, May 30, 2013 at 09:32:19PM +0300, Andy Shevchenko wrote:
Here is a set of small independent patches that clean up or fix minor
things
across DMA slave
From: Hongbo Zhang hongbo.zh...@freescale.com
Hi Vinod, Dan, Leo and Scott, please have a look at these V2 patches.
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch set
adds support this DMA engine.
V2-V3 changes:
- edit
Until now, the MSI architecture-specific functions could be overloaded
using a fairly complex set of #define and compile-time
conditionals. In order to prepare for the introduction of the msi_chip
infrastructure, it is desirable to switch all those functions to use
the 'weak' mechanism. This
Now that we have weak versions for each of the PCI MSI architecture
functions, we can actually build the MSI support for all platforms,
regardless of whether they provide or not architecture-specific
versions of those functions. For this reason, the ARCH_SUPPORTS_MSI
hidden kconfig boolean becomes
On Jul 5, 2013, at 1:27 AM, hongbo.zh...@freescale.com
hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch add
the device tree nodes for them.
Signed-off-by: Hongbo Zhang
On Jul 5, 2013, at 1:27 AM, hongbo.zh...@freescale.com
hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch add
the device tree nodes for them.
Signed-off-by: Hongbo Zhang
On 07/15/2013 03:45:36 AM, David Laight wrote:
+#define MFTB(dest, scratch1, scratch2)\
+90: mftbu scratch1; \
+ mftbl dest; \
+ mftbu scratch2; \
+ cmpwscratch1,scratch2; \
+ bne 90b;\
+
The patchset adds compression support to pstore.
As the non-volatile storage space is limited, adding compression
support results in capturing more data within limited space.
Size of dmesg file in a powerpc/pseries box with nvram's
oops partition (to store oops-log) size 4k:
Without
On 07/15/2013 01:03:22 AM, Aneesh Kumar K.V wrote:
Scott Wood scottw...@freescale.com writes:
diff --git a/arch/powerpc/platforms/Kconfig.cputype
b/arch/powerpc/platforms/Kconfig.cputype
index ae0aaea..7f0e2e5 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++
(De)compression support is provided in pstore in subsequent patches which
needs an additional argument 'compressed' to determine if the data
is compressed or not. This patch will take care of removing (de)compression
in nvram with pstore which was making use of 'hsize' argument in pstore write
as
Addition of new argument 'compressed' in the write call back will
help the backend to know if the data passed from pstore is compressed
or not (In case where compression fails.). If compressed, the backend
can add a tag indicating the data is compressed while writing to
persistent store.
Pstore will make use of deflate and inflate algorithm to compress and decompress
the data. So when Pstore is enabled select zlib_deflate and zlib_inflate.
Signed-off-by: Aruna Balakrishnaiah ar...@linux.vnet.ibm.com
---
fs/pstore/Kconfig |2 ++
1 file changed, 2 insertions(+)
diff --git
Backends will set the flag 'compressed' after reading the log from
persistent store to indicate the data being returned to pstore is
compressed or not.
Signed-off-by: Aruna Balakrishnaiah ar...@linux.vnet.ibm.com
---
arch/powerpc/platforms/pseries/nvram.c |2 +-
drivers/acpi/apei/erst.c
Add compression support to pstore which will help in capturing more data.
Initially, pstore will make a call to kmsg_dump with a bigger buffer
and will pass the size of bigger buffer to kmsg_dump and then compress
the data to registered buffer of registered size.
In case compression fails, pstore
In case decompression fails, add a .enc.z to indicate the file has
compressed data. This will help user space utilities to figure
out the file contents.
Signed-off-by: Aruna Balakrishnaiah ar...@linux.vnet.ibm.com
---
fs/pstore/inode.c|9 +
fs/pstore/internal.h |5 +++--
Based on the flag 'compressed' set or not, pstore will decompress the
data returning a plain text file. If decompression fails for a particular
record it will have the compressed data in the file which can be
decompressed with 'openssl' command line tool.
Signed-off-by: Aruna Balakrishnaiah
If data returned from pstore is compressed, nvram's write callback
will add a flag ERR_TYPE_KERNEL_PANIC_GZ indicating the data is compressed
while writing to nvram. If the data read from nvram is compressed, nvram's
read callback will set the flag 'compressed'. The patch adds backward
In pstore write, set the section type to CPER_SECTION_TYPE_DMESG_COMPR
if the data is compressed. In pstore read, read the section type and
update the 'compressed' flag accordingly.
Signed-off-by: Aruna Balakrishnaiah ar...@linux.vnet.ibm.com
---
drivers/acpi/apei/erst.c | 13 -
1
In pstore write, Efi will add a character 'C'(compressed) or
D'(decompressed) in its header while writing to persistent store.
In pstore read, read the header and update the 'compressed' flag
accordingly.
Signed-off-by: Aruna Balakrishnaiah ar...@linux.vnet.ibm.com
---
In pstore write, add character 'C'(compressed) or 'D'(decompressed)
in the header while writing to Ram persistent buffer. In pstore read,
read the header and update the 'compressed' flag accordingly.
Signed-off-by: Aruna Balakrishnaiah ar...@linux.vnet.ibm.com
---
fs/pstore/ram.c | 36
On 07/15/2013 08:35:07 AM, Kumar Gala wrote:
On Jul 5, 2013, at 1:27 AM, hongbo.zh...@freescale.com
hongbo.zh...@freescale.com wrote:
+dma0: dma@100300 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,elo3-dma;
why does this require a new compatible?
The binding has
On 07/15/2013 05:34:58 AM, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this
patch add
the device tree nodes for them.
Signed-off-by: Hongbo Zhang hongbo.zh...@freescale.com
---
clocks need to get prepared before they can get enabled,
fix the MPC512x PSC SPI master's initialization
Signed-off-by: Gerhard Sittig g...@denx.de
---
drivers/spi/spi-mpc512x-psc.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-mpc512x-psc.c
this series introduces support for the common clock framework (CCF,
COMMON_CLK Kconfig option) in the PowerPC based MPC512x platform, a
resulting debugfs clk_summary is at the end of the message after the
stats
although the series does touch several subsystems -- serial, spi, net
(can, fs_enet),
must prepare clocks before enabling them, unprepare after disable
Signed-off-by: Gerhard Sittig g...@denx.de
---
drivers/mtd/nand/mpc5121_nfc.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index
reword the clock control module's registers declaration such that the
MCLK related registers form an array and get indexed by PSC number
this change is in preparation to COMMON_CLK support for the MPC512x
platform, the changed declaration remains neutral to existing code since
the PSC and MSCAN
clocks need to get prepared before they can get enabled, and after
disabling them they can get unprepared
Signed-off-by: Gerhard Sittig g...@denx.de
---
drivers/tty/serial/mpc52xx_uart.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/mpc52xx_uart.c
prepare C preprocessor support when processing MPC512x DTS files
- switch from DTS syntax to CPP syntax for include specs
- create a symlink such that DTS processing can reference includes
Signed-off-by: Gerhard Sittig g...@denx.de
---
arch/powerpc/boot/dts/ac14xx.dts |2 +-
the common clock drivers were motivated/initiated by ARM development
and apparently assume little endian peripherals
wrap register/peripherals access in the common code (div, gate, mux)
in preparation of adding COMMON_CLK support for other platforms
Signed-off-by: Gerhard Sittig g...@denx.de
---
introduce a dt-bindings/ header file for MPC512x clocks,
providing symbolic identifiers for those SoC clocks which
clients will reference from their device tree nodes
Signed-off-by: Gerhard Sittig g...@denx.de
---
include/dt-bindings/clock/mpc512x-clock.h | 59 +
1
this addresses the clock driver aka provider's side of clocks
- prepare for future 'clks ID' phandle references for device tree
based clock lookup in client drivers
- introduce a 'clocks' subtree with an 'osc' node for the crystal
or oscillator SoC input (fixed frequency)
- provide default
this addresses the client side of device tree based clock lookups:
add clock specifiers to the mbx, nfc, mscan, sdhc, i2c, axe, diu,
viu, mdio, fec, usb, pata, psc, psc fifo, and pci nodes in the
shared mpc5121.dtsi include
these specs map 'clock-names' encoded in drivers to their respective
this change introduces a clock infrastructure implementation for the
MPC512x PowerPC platform which follows the COMMON_CLK approach and uses
common clock drivers shared with other platforms
this driver implements the publicly announced set of clocks (which can
get referenced by means of symbolic
add a comment about the magic of deriving an MSCAN component index
from the peripheral's physical address / register offset
Signed-off-by: Gerhard Sittig g...@denx.de
---
drivers/net/can/mscan/mpc5xxx_can.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
after PSC related clock specifiers were added to the device tree,
the former 'psc%d_mclk' isn't needed any longer to lookup clock items
Signed-off-by: Gerhard Sittig g...@denx.de
---
drivers/spi/spi-mpc512x-psc.c |4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git
extend the mscan(4) driver with alternative support for the COMMON_CLK
approach which is an option in the MPC512x platform, keep the existing
clock support implementation in place since the driver is shared with
other MPC5xxx SoCs which don't have common clock support
one byproduct of this change
adapt the DIU clock initialization to the COMMON_CLK approach: device
tree based clock lookup, prepare and unprepare for clocks, work with
frequencies not dividers, call the appropriate clk_*() routines and
don't access CCM registers, remove the pre-enable workaround in the
platform's clock driver
On Mon, Jul 15, 2013 at 08:47:34PM +0200, Gerhard Sittig wrote:
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 6d55eb2..2c07061 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -104,7 +104,7 @@ static unsigned long
On Mon, Jul 15, 2013 at 08:47:30PM +0200, Gerhard Sittig wrote:
clocks need to get prepared before they can get enabled,
fix the MPC512x PSC SPI master's initialization
Signed-off-by: Gerhard Sittig g...@denx.de
---
drivers/spi/spi-mpc512x-psc.c |2 +-
1 file changed, 1 insertion(+), 1
with device tree based clock lookup, the MCLK name no longer
depends on the PSC index
Signed-off-by: Gerhard Sittig g...@denx.de
---
drivers/tty/serial/mpc52xx_uart.c |8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/tty/serial/mpc52xx_uart.c
On Mon, Jul 15, 2013 at 11:46:01PM +0200, Gerhard Sittig wrote:
with device tree based clock lookup, the MCLK name no longer
depends on the PSC index
Signed-off-by: Gerhard Sittig g...@denx.de
---
drivers/tty/serial/mpc52xx_uart.c |8 ++--
1 file changed, 2 insertions(+), 6
On 07/15/2013 11:53:54 AM, Scott Wood wrote:
On 07/15/2013 03:45:36 AM, David Laight wrote:
Also, if the high word changes, there is no need to loop.
Just return the second value with a low word of zero
(the returned count happened while the function was active).
That would be more
Hello-
The Espresso CPU within the Nintendo Wii U is a PowerPC 750 based CPU with
three cores. I was wondering if anyone knew of any way to enable CONFIG_SMP
on the Linux kernel without preventing the kernel from booting.
http://en.wikipedia.org/wiki/Espresso_(microprocessor)
Hello, this is our custom board's u-boot:
U-Boot 2009.08 (Apr 19 2010 - 05:35:19)
CPU: MPC5200B v2.2, Core v1.4 at 132 MHz
Bus 132 MHz, IPB 132 MHz, PCI 66 MHz
Board: Ran Controller Board
I2C: 85 kHz, ready
DRAM: 128 MB
FLASH: 64 MB
We have 1:1 CPU:bus
This is to reserve a capablity number for upcoming support
of H_PUT_TCE_INDIRECT and H_STUFF_TCE pseries hypercalls
which support mulptiple DMA map/unmap operations per one call.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
Changes:
2013/07/16:
* changed the number
Signed-off-by:
The changes are:
1. rebased on v3.11-rc1 so the capability numbers changed again
2. fixed multiple comments from maintainers
3. KVM: PPC: Add support for IOMMU in-kernel handling is split into
2 patches, the new one is powerpc/iommu: rework to support realmode.
4. IOMMU_API is now always enabled
This is to reserve a capablity number for upcoming support
of VFIO-IOMMU DMA operations in real mode.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
Changes:
2013/07/16:
* changed the number
2013/07/11:
* changed order in a file, added comment about a gap in ioctl number
Signed-off-by:
The current VFIO-on-POWER implementation supports only user mode
driven mapping, i.e. QEMU is sending requests to map/unmap pages.
However this approach is really slow, so we want to move that to KVM.
Since H_PUT_TCE can be extremely performance sensitive (especially with
network adapters where
VFIO is designed to be used via ioctls on file descriptors
returned by VFIO.
However in some situations support for an external user is required.
The first user is KVM on PPC64 (SPAPR TCE protocol) which is going to
use the existing VFIO groups for exclusive access in real/virtual mode
on a host
The existing TCE machine calls (tce_build and tce_free) only support
virtual mode as they call __raw_writeq for TCE invalidation what
fails in real mode.
This introduces tce_build_rm and tce_free_rm real mode versions
which do mostly the same but use Store Doubleword Caching Inhibited
Indexed
This adds real mode handlers for the H_PUT_TCE_INDIRECT and
H_STUFF_TCE hypercalls for user space emulated devices such as IBMVIO
devices or emulated PCI. These calls allow adding multiple entries
(up to 512) into the TCE table in one call which saves time on
transition to/from real mode.
This
It does not make much sense to have KVM in book3s-64bit and
not to have IOMMU bits for PCI pass through support as it costs little
and allows VFIO to function on book3s-kvm.
Having IOMMU_API enabled will make it unnecessary to have a lot of
IOMMU_API enabled, those files only accelerate user
The TCE tables handling may differ for real and virtual modes so
additional ppc_md.tce_build_rm/ppc_md.tce_free_rm/ppc_md.tce_flush_rm
handlers were introduced earlier.
So this adds the following:
1. support for the new ppc_md calls;
2. ability to iommu_tce_build to process mupltiple entries per
This adds special support for huge pages (16MB) in real mode.
The reference counting cannot be easily done for such pages in real
mode (when MMU is off) so we added a hash table of huge pages.
It is populated in virtual mode and get_page is called just once
per a huge page. Real mode handlers
This allows the host kernel to handle H_PUT_TCE, H_PUT_TCE_INDIRECT
and H_STUFF_TCE requests targeted an IOMMU TCE table without passing
them to user space which saves time on switching to user space and back.
Both real and virtual modes are supported. The kernel tries to
handle a TCE request in
Hi Ben.
Thanks for the information. Your reply is eagerly awaited.
Regards.
On Jul 15, 2013 3:50 AM, Benjamin Herrenschmidt [via linuxppc]
ml-node+s10917n7373...@n7.nabble.com wrote:
On Fri, 2013-07-12 at 04:38 -0700, JiveTalkin wrote:
Moderator..can you change the subject of this to
The SOFT_DISABLE_INTS seems an odd name for something that updates the
software state to be consistent with interrupts being hard disabled, so
rename SOFT_DISABLE_INTS with RECONCILE_IRQ_STATE to avoid this confusion.
Signed-off-by: Tiejun Chen tiejun.c...@windriver.com
---
Ben,
Looks currently
Hi, Anton
You mean get voltage support from DTS?
Or get voltage both from DTS and host capacity register?
Thanks.
Regards
Haijun.
-Original Message-
From: linux-mmc-ow...@vger.kernel.org [mailto:linux-mmc-
ow...@vger.kernel.org] On Behalf Of Anton Vorontsov
Sent: Saturday, July
On Tue, Jul 16, 2013 at 03:11:47AM +, Zhang Haijun-B42677 wrote:
Hi, Anton
You mean get voltage support from DTS?
Or get voltage both from DTS and host capacity register?
The logic might be that you first check device-tree, if it specifies
voltage ranges, assume that DTS knows better,
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