From: Bharat Bhushan bharat.bhus...@freescale.com
First patch is a typo fix where book3e define _PAGE_LENDIAN while it
should be defined as _PAGE_ENDIAN. This seems to show that this is never
exercised :-)
Second and third patch is to allow guest controlling G-Guarded and E-Endian
TLB
For booke3e _PAGE_ENDIAN is not defined. Infact what is defined
is _PAGE_LENDIAN which is wrong and that should be _PAGE_ENDIAN.
There are no compilation errors as
arch/powerpc/include/asm/pte-common.h defines _PAGE_ENDIAN to 0
as it is not defined anywhere.
Signed-off-by: Bharat Bhushan
G bit in MAS2 indicates whether the page is Guarded.
There is no reason to stop guest setting G, so allow him.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v1-v5
- no change
arch/powerpc/kvm/e500.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git
E bit in MAS2 bit indicates whether the page is accessed
in Little-Endian or Big-Endian byte order.
There is no reason to stop guest setting E, so allow him.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v1-v5
- no change
arch/powerpc/kvm/e500.h |2 +-
1 files changed, 1
On booke, struct tlbe_ref contains host tlb mapping information
(pfn: for guest-pfn to pfn, flags: attribute associated with this mapping)
for a guest tlb entry. So when a guest creates a TLB entry then
struct tlbe_ref is set to point to valid pfn and set attributes in
flags field of the above
lookup_linux_pte() was searching for a pte and also sets access
flags is writable. This function now searches only pte while
access flag setting is done explicitly.
This pte lookup is not kvm specific, so moved to common code (asm/pgtable.h)
My Followup patch will use this on booke.
KVM uses same WIM tlb attributes as the corresponding qemu pte.
For this we now search the linux pte for the requested page and
get these cache caching/coherency attributes from pte.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v4-v5
- No change
This patch adds interface to get following information
- Number of MSI regions (which is number of MSI banks for powerpc).
- Get the region address range: Physical page which have the
address/addresses used for generating MSI interrupt
and size of the page.
These are required to
From: Bharat Bhushan bharat.bhus...@freescale.com
returns the iommu_domain of the requested device for fsl pamu.
Use PCI controller dev struct for pci devices as current LIODN schema
assign LIODN to PCI controller not PCI device. This will be corrected
with proper LIODN schema.
Signed-off-by:
This api return the iommu domain to which the device is attached.
The iommu_domain is required for making API calls related to iommu.
Follow up patches which use this API to know iommu maping.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
drivers/iommu/iommu.c | 10 ++
From: Bharat Bhushan bharat.bhus...@freescale.com
This patchset adds support for vfio-pci with Freescale
IOMMU (PAMU- Peripheral Access Management Unit)
The Freescale PAMU is an aperture-based IOMMU with the following
characteristics. Each device has an entry in a table in memory
describing the
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
drivers/vfio/pci/vfio_pci_rdwr.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c
index 210db24..8a8156a 100644
---
If the device is attached with iommu domain then set MSI address
to the iova configured in PAMU.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
arch/powerpc/sysdev/fsl_msi.c | 56 +++-
1 files changed, 54 insertions(+), 2 deletions(-)
diff
Some function defined in vfio_iommu_type1.c were common and
we want to use these for FSL IOMMU (PAMU) and iommu-none driver.
So some of them are moved to vfio_iommu_common.c
I think we can do more of that but we will take this step by step.
Signed-off-by: Bharat Bhushan
This patch adds vfio iommu support for Freescale IOMMU
(PAMU - Peripheral Access Management Unit).
The Freescale PAMU is an aperture-based IOMMU with the following
characteristics. Each device has an entry in a table in memory
describing the iova-phys mapping. The mapping has:
-an overall
On 09/14/2013 06:19 AM, Sukadev Bhattiprolu wrote:
+static void power7_get_mem_data_src(union perf_mem_data_src *dsrc,
+ struct pt_regs *regs)
+{
+ u64 idx;
+ u64 mmcra = regs-dsisr;
+ u64 addr;
+ int ret;
+ unsigned int instr;
+
+ if (mmcra
The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking telecommunications.
T1042 personality is a reduced personality of T1040 without Integrated
T1040 supports both 32 64 bit kernel.
so enable T1040QDS by default in the config files.
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
Branch next
Changes for v2: Sending as it is
Changes for v3:
On Tue, Sep 17, 2013 at 12:01 PM, Geert Uytterhoeven
ge...@linux-m68k.org wrote:
This is a preliminary set of patches to add kexec support for m68k.
- [PATCH 1/3] m68k: Add preliminary kexec support
- [PATCH 2/3] m68k: Add support to export bootinfo in procfs
- [PATCH 3/3] [RFC] m68k:
Under heavy (DLPAR?) stress, we tripped this panic() in
arch/powerpc/kernel/iommu.c::iommu_init_table():
page = alloc_pages_node(nid, GFP_ATOMIC, get_order(sz));
if (!page)
panic(iommu_init_table: Can't allocate %ld bytes\n,
sz);
Before the panic() we got a page
On Thu, Sep 19, 2013 at 4:00 AM, Prabhakar Kushwaha
prabha...@freescale.com wrote:
- Video
- DIU supports video at up to 1280x1024x32bpp
You mention DIU support, except there's no DIU enablement in the
platform file. You need the T104x equivalent of
p1022ds_set_pixel_clock() and the
On Thu, 2013-09-19 at 11:32 +0530, Bharat Bhushan wrote:
On booke, struct tlbe_ref contains host tlb mapping information
(pfn: for guest-pfn to pfn, flags: attribute associated with this mapping)
for a guest tlb entry. So when a guest creates a TLB entry then
struct tlbe_ref is set to point to
This started out as a request to look at the DMA mask situation, and how
to solve the issues which we have on ARM - notably how the DMA mask
should be setup.
However, I started off reviewing how the dma_mask and coherent_dma_mask
was being used, and what I found was rather messy, and in some
On Thu, Sep 19, 2013 at 11:20:22AM +0200, Geert Uytterhoeven wrote:
On Tue, Sep 17, 2013 at 12:01 PM, Geert Uytterhoeven
ge...@linux-m68k.org wrote:
This is a preliminary set of patches to add kexec support for m68k.
- [PATCH 1/3] m68k: Add preliminary kexec support
- [PATCH 2/3]
On Thu, 2013-09-19 at 22:25 +0100, Russell King wrote:
Provide a helper to set both the DMA and coherent DMA masks to the
same value - this avoids duplicated code in a number of drivers,
sometimes with buggy error handling, and also allows us identify
which drivers do things differently.
Hi Tabi,
-Original Message-
From: Timur Tabi [mailto:ti...@tabi.org]
Sent: Friday, September 20, 2013 2:03 AM
To: Kushwaha Prabhakar-B32579
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Jain Priyanka-
B32167; Aggrwal Poonam-B10812
Subject: Re: [PATCH 1/2][v3]
The fallback to 32-bit DMA mask is rather odd:
err = dma_set_mask(pdev-dev, DMA_BIT_MASK(64));
if (!err) {
err = dma_set_coherent_mask(pdev-dev, DMA_BIT_MASK(64));
if (!err)
pci_using_dac = 1;
} else {
The fallback to 32-bit DMA mask is rather odd:
err = dma_set_mask(pdev-dev, DMA_BIT_MASK(64));
if (!err) {
err = dma_set_coherent_mask(pdev-dev, DMA_BIT_MASK(64));
if (!err)
pci_using_dac = 1;
} else {
The fallback to 32-bit DMA mask is rather odd:
err = dma_set_mask(pdev-dev, DMA_BIT_MASK(64));
if (!err) {
err = dma_set_coherent_mask(pdev-dev, DMA_BIT_MASK(64));
if (!err)
pci_using_dac = 1;
} else {
The fallback to 32-bit DMA mask is rather odd:
if (!dma_set_mask(pdev-dev, DMA_BIT_MASK(64))
!dma_set_coherent_mask(pdev-dev, DMA_BIT_MASK(64))) {
*using_dac = true;
} else {
err = dma_set_mask(pdev-dev, DMA_BIT_MASK(32));
The fallback to 32-bit DMA mask is rather odd:
err = dma_set_mask(pdev-dev, DMA_BIT_MASK(64));
if (!err) {
err = dma_set_coherent_mask(pdev-dev, DMA_BIT_MASK(64));
if (!err)
pci_using_dac = 1;
} else {
Provide a helper to set both the DMA and coherent DMA masks to the
same value - this avoids duplicated code in a number of drivers,
sometimes with buggy error handling, and also allows us identify
which drivers do things differently.
Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk
---
The fallback to 32-bit DMA mask is rather odd:
if (!dma_set_mask(pdev-dev, DMA_BIT_MASK(64))
!dma_set_coherent_mask(pdev-dev, DMA_BIT_MASK(64))) {
pci_using_dac = 1;
} else {
err = dma_set_mask(pdev-dev, DMA_BIT_MASK(32));
The fallback to 32-bit DMA mask is rather odd:
if (!dma_set_mask(pdev-dev, DMA_BIT_MASK(64))
!dma_set_coherent_mask(pdev-dev, DMA_BIT_MASK(64))) {
pci_using_dac = 1;
} else {
err = dma_set_mask(pdev-dev, DMA_BIT_MASK(32));
Kushwaha Prabhakar-B32579 wrote:
My primary object is to put base patch in Linux. once it done other things can
be enabled one by one.
Any features which are not enabled must be specified in the patch
description. The patch says that the board supports DIU, but the code
doesn't, so that's
-Original Message-
From: Wood Scott-B07421
Sent: Friday, September 20, 2013 2:38 AM
To: Bhushan Bharat-R65777
Cc: b...@kernel.crashing.org; ag...@suse.de; pau...@samba.org;
k...@vger.kernel.org; kvm-...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
Bhushan Bharat-R65777
On booke, struct tlbe_ref contains host tlb mapping information
(pfn: for guest-pfn to pfn, flags: attribute associated with this mapping)
for a guest tlb entry. So when a guest creates a TLB entry then
struct tlbe_ref is set to point to valid pfn and set attributes in
flags field of the above
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