Commit 8f619b5429d9 (powerpc/ppc64: Do not turn AIL (reloc-on
interrupts) too early) added code to set the AIL bit in the LPCR
without checking whether the kernel is running in hypervisor mode.
The result is that when the kernel is running as a guest (i.e.,
under PowerKVM or PowerVM), the
Benjamin Herrenschmidt b...@kernel.crashing.org wrote:
Turn them on at the same time as we allow MSR_IR/DR in the paca
kernel MSR, ie, after the MMU has been setup enough to be able
to handle relocated access to the linear mapping.
Signed-off-by: Benjamin Herrenschmidt
On 04/10/2014 08:05 PM, Andy Shevchenko wrote:
On Thu, 2014-04-10 at 15:10 +0800, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
This patch adds suspend resume functions for Freescale DMA driver.
.prepare callback is used to stop further descriptors from being
On 04/10/2014 07:56 PM, Andy Shevchenko wrote:
On Thu, 2014-04-10 at 15:10 +0800, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
Fix the potential risk when enable config NET_DMA and ASYNC_TX. Async_tx is
lack of support in current release process of dma
On 04/10/2014 07:29 PM, Andy Shevchenko wrote:
On Thu, 2014-04-10 at 15:10 +0800, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
There are several places where descriptors are freed using identical code.
This patch puts this code into a function to reduce code
From: Xuelin Shi xuelin@freescale.com
The RaidEngine is a new FSL hardware used for Raid5/6 acceration.
This patch enables the RaidEngine functionality and provides
hardware offloading capability for memcpy, xor and pq computation.
It works with async_tx.
Signed-off-by: Harninder Rai
Hi Dan,
With https://patchwork.kernel.org/patch/3863711/ applied, the issue disappeared.
Thanks,
Xuelin Shi
-Original Message-
From: dan.j.willi...@gmail.com [mailto:dan.j.willi...@gmail.com] On Behalf Of
Dan Williams
Sent: 2014年4月10日 12:02
To: Shi Xuelin-B29237
Cc: Koul, Vinod;
On 04/11/2014 04:00 PM, Hongbo Zhang wrote:
On 04/10/2014 07:56 PM, Andy Shevchenko wrote:
On Thu, 2014-04-10 at 15:10 +0800, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
Fix the potential risk when enable config NET_DMA and ASYNC_TX.
Async_tx is
lack of
The runlatch bits with their value indicated by CTRL_RUNLATCH are set and
cleared in the SPRN_CTRL registers to indicate a busy and idle cpu
respectively. This is currently being done in the cpuidle path of the host.
But needs to be taken care of in hotplug and kvm scenarios. This patchset
is
By doing this, the driver can drop around 50 lines and become neater.
Signed-off-by: Nicolin Chen guangyu.c...@freescale.com
---
sound/soc/fsl/fsl_sai.c | 101
1 file changed, 25 insertions(+), 76 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c
The runlatch bits with their value indicated by CTRL_RUNLATCH are set and
cleared in the SPRN_CTRL registers to indicate a busy and idle cpu
respectively. This is currently being done in the cpuidle path of the host.
But needs to be taken care of in hotplug and kvm scenarios. This patchset
is
Up until now we have been setting the runlatch bits for a busy CPU and
clearing it when a CPU enters idle state. The runlatch bit has thus
been consistent with the utilization of a CPU as long as the CPU is online.
However when a CPU is hotplugged out the runlatch bit is not cleared. It
needs to
The secondary threads in the core are kept offline before launching guests
in kvm on powerpc: 371fefd6f2dc4666:KVM: PPC: Allow book3s_hv guests to use
SMT processor modes.
Hence their runlatch bits are cleared. When the secondary threads are called
in to start a guest, their runlatch bits need to
When the guest cedes the vcpu or the vcpu has no guest to
run it naps. Clear the runlatch bit of the vcpu before
napping to indicate an idle cpu.
Signed-off-by: Preeti U Murthy pre...@linux.vnet.ibm.com
Acked-by: Paul Mackerras pau...@samba.org
Reviewed-by: Srivatsa S. Bhat
When we mark pte with _PAGE_NUMA we already call
mmu_notifier_invalidate_range_start
and mmu_notifier_invalidate_range_end, which will mark existing guest hpte
entry as HPTE_V_ABSENT. Now we need to do that when we are inserting new
guest hpte entries.
Signed-off-by: Liu Ping Fan
On 11.04.2014, at 13:45, Liu Ping Fan pingf...@linux.vnet.ibm.com wrote:
When we mark pte with _PAGE_NUMA we already call
mmu_notifier_invalidate_range_start
and mmu_notifier_invalidate_range_end, which will mark existing guest hpte
entry as HPTE_V_ABSENT. Now we need to do that when we are
Patch ASoC: fsl_sai: Fix buggy configurations in trigger() doesn't entirely
fix the condition: FRDE of the current substream direction is being cleared
while the code is still using the non-updated one.
Thus this patch fixes this issue by checking the opposite one's FRDE alone
since the current
A few more comments:
On Fri, Apr 11, 2014 at 12:41 AM, xuelin@freescale.com wrote:
From: Xuelin Shi xuelin@freescale.com
The RaidEngine is a new FSL hardware used for Raid5/6 acceration.
This patch enables the RaidEngine functionality and provides
hardware offloading capability for
On Fri, Apr 11, 2014 at 10:42 AM, Dan Williams dan.j.willi...@intel.com wrote:
A few more comments:
On Fri, Apr 11, 2014 at 12:41 AM, xuelin@freescale.com wrote:
From: Xuelin Shi xuelin@freescale.com
The RaidEngine is a new FSL hardware used for Raid5/6 acceration.
This patch
This patch converts GE I/O FPGA GPIO driver to platform driver.
Signed-off-by: Alexander Shiyan shc_w...@mail.ru
---
drivers/gpio/gpio-ge.c | 174 +++--
1 file changed, 53 insertions(+), 121 deletions(-)
diff --git a/drivers/gpio/gpio-ge.c
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