On Mon, Mar 23, 2015 at 12:24:00PM +, Mel Gorman wrote:
These are three follow-on patches based on the xfsrepair workload Dave
Chinner reported was problematic in 4.0-rc1 due to changes in page table
management -- https://lkml.org/lkml/2015/3/1/226.
Much of the problem was reduced by
On Tue, 2015-03-24 at 09:56 +0530, Anshuman Khandual wrote:
On 03/24/2015 07:34 AM, Michael Ellerman wrote:
On Fri, 2015-03-20 at 14:34 +0530, Anshuman Khandual wrote:
On 03/19/2015 10:13 AM, Sam Bobroff wrote:
This patch changes the syscall handler to doom (tabort) active
transactions
On Tue, 2015-03-24 at 12:18 +0530, Hemant Kumar wrote:
Hi Michael,
These patches were posted a month back. We don't have any review
comments to handle at this time. Can you pull these patches to your tree?
Please, do let me know if you want me to rebase these patches to a
different tree
After previous discussions regarding the subject [1][2], there's no clear
explanation or reason why the call was needed in the first place. The sensible
argument is some sort of synchronization between the CPU and the MPIC, which
hasn't been pointed out precisely and is no longer required (at
POWER7 has a dedicated stream prefetcher that is pre-programmed via
dcbt rX,rY,0b010?0 instructions in the beginning of vmx_copy.
e6500 has no such prefetcher, so we revert to using regular dcbt
instructions in-loop:
1. at __copy_tofrom_user_power7 entry, we prefetch the first
src and dest lines
The innermost copyloops were optimized for POWER7's 128-byte cacheline.
This patch adds optimization for the e6500, which has a 64-byte
cacheline.
We basically do this by stripping loop bodies using L1_CACHE_BYTES
ifdeferry, replace 128 with L1_CACHE_BYTES, and 7's with L1_CACHE_SHIFTs.
We also
From: Sowmini Varadhan sowmini.varad...@oracle.com
Date: Tue, 24 Mar 2015 13:10:27 -0400
Deltas from patchv5:
- removed iommu_tbl_ops, and instead pass the -flush_all as
an indirection to iommu_tbl_pool_init()
- only invoke -flush_all when there is no large_pool, based on
the assumption
This enables the VMX/ALTIVEC optimised copy-to/from-user code in
arch/powerpc/lib/copyuser_power7.S. The e6500 does, and the e5500
does not, have ALTIVEC.
Signed-off-by: Kim Phillips kim.phill...@freescale.com
---
arch/powerpc/include/asm/cputable.h | 2 +-
1 file changed, 1 insertion(+), 1
On Tue, 2015-03-24 at 11:34 +0800, Yijing Wang wrote:
Now we could use pci_scan_host_bridge() to scan
pci buses, provide powerpc specific pci_host_bridge_ops.
Signed-off-by: Yijing Wang wangyij...@huawei.com
CC: Benjamin Herrenschmidt b...@kernel.crashing.org
CC:
On Tue, Mar 24, 2015 at 10:51:41PM +1100, Dave Chinner wrote:
On Mon, Mar 23, 2015 at 12:24:00PM +, Mel Gorman wrote:
These are three follow-on patches based on the xfsrepair workload Dave
Chinner reported was problematic in 4.0-rc1 due to changes in page table
management --
On Tue, 2015-03-24 at 21:49 +0200, Alex Dowad wrote:
On 20/03/15 01:54, Michael Ellerman wrote:
On Thu, 2015-03-19 at 09:22 +0200, Alex Dowad wrote:
On 19/03/15 08:45, Michael Ellerman wrote:
On Fri, 2015-13-03 at 18:14:46 UTC, Alex Dowad wrote:
The 'arg' argument to copy_thread() is only
On Tue, 2015-02-03 at 12:39 +0100, Christophe Leroy wrote:
csum_tcpudp_magic() is only a few instructions, and does not modifies any
other
register than the returned result. So it is not worth having it as a separate
function and suffer function branching and saving of volatile registers.
On Tue, 2015-03-24 at 11:52 +1100, Cyril Bur wrote:
On Wed, 2015-03-04 at 12:22 -0800, Tyrel Datwyler wrote:
During suspend/migration operation we must wait for the VASI state reported
by the hypervisor to become Suspending prior to making the ibm,suspend-me
RTAS call. Calling routines to
On Tue, Feb 03, 2015 at 12:39:27PM +0100, LEROY Christophe wrote:
The C version of csum_add() as defined in include/net/checksum.h gives the
following assembly:
0: 7c 04 1a 14 add r0,r4,r3
4: 7c 64 00 10 subfc r3,r4,r0
8: 7c 63 19 10
On Fri, 2015-03-13 at 10:34 +1100, Michael Ellerman wrote:
On Thu, 2015-03-12 at 16:24 +0100, Christophe Leroy wrote:
Two config options exist to define powerpc MPC8xx:
* CONFIG_PPC_8xx
* CONFIG_8xx
In addition, CONFIG_PPC_8xx also defines CONFIG_CPM1 as
communication co-processor
On Tue, Feb 03, 2015 at 12:39:27PM +0100, LEROY Christophe wrote:
On PPC_8xx, lwz has a 2 cycles latency, and branching also takes 2 cycles.
As the size of the header is minimum 5 words, we can unroll the loop for the
first words to reduce number of branching, and we can re-order the
On Fri, 2015-27-02 at 22:22:54 UTC, Yannick Guerrini wrote:
Change 'Kenrel' to 'Kernel'
Signed-off-by: Yannick Guerrini yguerr...@tomshardware.fr
---
arch/powerpc/include/asm/smu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
If you're going to send spelling fix patches, please
On Tue, 2015-03-24 at 19:45 -0500, Scott Wood wrote:
On Fri, 2015-03-13 at 10:34 +1100, Michael Ellerman wrote:
On Thu, 2015-03-12 at 16:24 +0100, Christophe Leroy wrote:
Two config options exist to define powerpc MPC8xx:
* CONFIG_PPC_8xx
* CONFIG_8xx
In addition, CONFIG_PPC_8xx
On Tue, 2015-24-03 at 12:33:22 UTC, Jan Stancek wrote:
One path in power_pmu_event_init() calls get_cpu_var(), but is
missing matching call to put_cpu_var(), which causes preemption
imbalance and crash in user-space:
Page fault in user mode with in_atomic() = 1 mm = c01fefa5a280
NIP
On Wed, 2015-03-18 at 16:04 +1100, Michael Ellerman wrote:
On Tue, 2015-03-17 at 11:35 +0530, Anshuman Khandual wrote:
On 03/17/2015 04:34 AM, Michael Ellerman wrote:
What are you seeing exactly?
I am running on a BE PKVM guest but compiling the test case on
a different BE machine
Previously, find_and_init_phbs() was used in both PowerNV and pSeries
setup. However, since RTAS support has been dropped from PowerNV, we
can move it into a platform-specific file.
This patch depends on the patch to drop RTAS support from PowerNV:
http://patchwork.ozlabs.org/patch/449316/
Signed-off-by: Daniel Axtens d...@axtens.net
---
arch/powerpc/platforms/powermac/pci.c | 17 +
arch/powerpc/platforms/powermac/pmac.h | 4
arch/powerpc/platforms/powermac/setup.c | 18 --
3 files changed, 21 insertions(+), 18 deletions(-)
diff --git
The only function that checks ppc_swiotlb_enable is swiotlb_subsys_init.
The code in fsl_pci.c is called well after that, so don't bother
changing it.
(ppc_swiotlb is usually set in swiotlb_detect_4g, which is called by
a number of arch initcalls.)
Signed-off-by: Daniel Axtens d...@axtens.net
pcibios_enable_device_hook returned an int. Every implementation
returned either -EINVAL or 0. The return value wasn't propagated by
the caller: any non-zero return value caused pcibios_enable_device
to return -EINVAL itself. Therefore, make the hook return a bool.
Signed-off-by: Daniel Axtens
Name the shim pci_window_alignment (rather than window_alignment)
to avoid clashing with window_alignment in drivers/pci/setup-bus.c
Signed-off-by: Daniel Axtens d...@axtens.net
---
arch/powerpc/include/asm/pci-bridge.h | 21 +
arch/powerpc/kernel/pci-common.c | 10
On Fri, 2015-03-20 at 16:34 +0530, Vasant Hegde wrote:
From: Anshuman Khandual khand...@linux.vnet.ibm.com
This patch implements LED driver for PowerNV platform using the existing
generic LED class framework. It registers classdev structures for all
individual LEDs detected on the system
This patch set moves some PCI controller operations out of ppc_md and
into a new pci_controller_ops struct.
This is desirable for systems with more than one type of PCI
controller. In particular, it's intended that this new interface will
be used by the CXL (aka CAPI) driver.
The design tries to
Signed-off-by: Daniel Axtens d...@axtens.net
---
arch/powerpc/include/asm/pci-bridge.h | 11 +++
arch/powerpc/kernel/pci-common.c | 3 +--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h
If a pci_controller_ops struct is provided to iommu_init_early_dart,
populate that with the DMA setup ops, rather than ppc_md. If NULL is
provided, populate ppc_md as before.
This also patches the call sites for Maple and Power Mac to pass
NULL, so existing behaviour is preserved.
The benefit of
Signed-off-by: Daniel Axtens d...@axtens.net
---
arch/powerpc/include/asm/pci-bridge.h | 17 +
arch/powerpc/kernel/pci-common.c | 7 +--
2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
On Thu, 2015-02-26 at 10:48 +0100, Thomas Haschka wrote:
Hello,
I hope I get it correct this time, thanks again.
Thanks. Sorry for the delay, I've been a bit swamped. I looked at your
code a bit more in depth and I would appreciate a couple more changes
if you don't mind:
.../...
We need to move the probe mode defines to pci-bridge.h from pci.h.
They are required by the shim in order to return a sensible default.
Previously, the were defined in pci.h, but pci.h includes pci-bridge.h
before the relevant #defines. This means the definitions are absent
if pci.h is included
On Thu, 2015-03-12 at 17:27 +1100, Michael Ellerman wrote:
The powernv code has some conditional support for running on bare metal
machines that have no OPAL firmware, but provide RTAS.
No released machines ever supported that, and even in the lab it was
just a transitional hack in the days
On Thu, 2015-03-19 at 15:15 +1100, Michael Ellerman wrote:
The celleb code has seen no actual development for ~7 years.
We (maintainers) have no access to test hardware, and it is highly
likely the code has bit-rotted.
As far as we're aware the hardware was never widely available, and is
swiotlb_late_init sets up platform specific hooks. It's not actually
a late initcall, but a subsys initcall, called much earlier.
Ideally we'd call it swiotlb_init, but that's taken.
Call it swiotlb_subsys_init for now.
(It will be refactored and renamed later.)
Signed-off-by: Daniel Axtens
Signed-off-by: Daniel Axtens d...@axtens.net
---
arch/powerpc/include/asm/pci-bridge.h | 14 ++
arch/powerpc/kernel/pci-common.c | 3 +--
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
Signed-off-by: Daniel Axtens d...@axtens.net
---
arch/powerpc/include/asm/pci-bridge.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h
index 546d036..3ab8a2d 100644
---
Signed-off-by: Daniel Axtens d...@axtens.net
---
arch/powerpc/include/asm/pci-bridge.h | 15 +++
arch/powerpc/kernel/pci-common.c | 5 ++---
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
Note that this conversion is only being done to consolidate the
code and ensure that the common code provides the sufficient
abstraction. It is not expected to result in any noticeable
performance improvement, as there is typically one ldc_iommu
per vnet_port, and each one has 8k entries, with a
Investigation of multithreaded iperf experiments on an ethernet
interface show the iommu-lock as the hottest lock identified by
lockstat, with something of the order of 21M contentions out of
27M acquisitions, and an average wait time of 26 us for the lock.
This is not efficient. A more scalable
From: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Geoff Thorpe geoff.tho...@freescale.com
Signed-off-by: Hai-Ying Wang haiying.w...@freescale.com
Signed-off-by: Chunhe Lan chunhe@freescale.com
Signed-off-by: Poonam Aggrwal
In iperf experiments running linux as the Tx side (TCP client) with
10 threads results in a severe performance drop when TSO is disabled,
indicating a weakness in the software that can be avoided by using
the scalable IOMMU arena DMA allocation.
Baseline numbers before this patch:
with default
On 20/03/15 01:54, Michael Ellerman wrote:
On Thu, 2015-03-19 at 09:22 +0200, Alex Dowad wrote:
On 19/03/15 08:45, Michael Ellerman wrote:
On Fri, 2015-13-03 at 18:14:46 UTC, Alex Dowad wrote:
The 'arg' argument to copy_thread() is only ever used when forking a new
kernel thread. Hence,
Hi Shuah,
Today's linux-next merge of the kselftest tree got a conflict in
tools/testing/selftests/powerpc/Makefile between commit a908f5de3b10
(selftests/powerpc: Rename TARGETS in powerpc selftests makefile)
from the powerpc-mpe tree and commit 6faeeea44b84 (selftests: Add
install support for
Hi Michael,
These patches were posted a month back. We don't have any review
comments to handle at this time. Can you pull these patches to your tree?
Please, do let me know if you want me to rebase these patches to a
different tree (like Arnaldo's/tip etc).
On 02/27/2015 03:13 PM, Hemant
One path in power_pmu_event_init() calls get_cpu_var(), but is
missing matching call to put_cpu_var(), which causes preemption
imbalance and crash in user-space:
Page fault in user mode with in_atomic() = 1 mm = c01fefa5a280
NIP = 3fff9bf2cae0 MSR = 90014280f032
Oops: Weird page
Hello Scott,
On 03/23/2015 06:30 PM, Scott Wood wrote:
On Thu, 2015-02-26 at 09:26 -0600, Emil Medve wrote:
From: Igal Liberman igal.liber...@freescale.com
Signed-off-by: Igal Liberman igal.liber...@freescale.com
---
arch/powerpc/boot/dts/fsl/b4si-post.dtsi| 11 +++
On Tue, 2015-03-24 at 11:23 +0530, Aneesh Kumar K.V wrote:
/* assume we don't have huge pages in vmalloc space... */
addr = (pte_pfn(*p) PAGE_SHIFT) | (addr ~PAGE_MASK);
+ local_irq_restore(flags);
return __va(addr);
}
This is called in real mode, I don't like the debug
On Tue, Mar 24, 2015 at 8:33 AM, Mel Gorman mgor...@suse.de wrote:
On Tue, Mar 24, 2015 at 10:51:41PM +1100, Dave Chinner wrote:
So it looks like the patch set fixes the remaining regression and in
2 of the four cases actually improves performance
\o/
W00t.
Linus, these three patches
On Tue, Mar 03, 2015 at 10:41:22PM +0200, Andy Shevchenko wrote:
This patch re-uses hsdev-dev which is allocated on heap. Therefore, the
private structure, which is global variable, is reduced by one field.
In one case ap-dev is used and there it seems to be right decision.
Signed-off-by:
Deltas from patchv5:
- removed iommu_tbl_ops, and instead pass the -flush_all as
an indirection to iommu_tbl_pool_init()
- only invoke -flush_all when there is no large_pool, based on
the assumption that large-pool usage is infrequently encountered.
Sowmini (2):
Break up monolithic iommu
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