Re: [PATCH v4 23/32] cxlflash: Fix function prolog parameters and return codes

On 26/09/15 09:18, Matthew R. Ochs wrote: Several function prologs have incorrect parameter names and return code descriptions. This can lead to confusion when reviewing the source and creates inaccurate documentation. To remedy, update the function prologs to properly reflect parameter names

Re: [PATCH v4 12/32] cxlflash: Fix to avoid spamming the kernel log

On 26/09/15 09:15, Matthew R. Ochs wrote: During run-time the driver can be very chatty and spam the system kernel log. Various print statements can be limited and/or moved to development-only mode. Additionally, numerous prints can be converted to trace the corresponding device. The following

Re: [PATCH v4 02/32] cxlflash: Replace magic numbers with literals

On 26/09/15 09:12, Matthew R. Ochs wrote: From: Manoj Kumar Magic numbers are not meaningful and can create confusion. As a remedy, replace them with descriptive literals. Replace 512 with literal MAX_SECTOR_UNIT. Replace 5 with literal CMD_RETRIES. Signed-off-by: Matthew

Re: [PATCH] perf record: Limit --intr-regs to platforms supporting PERF_REGS

On 2015/09/24 10:15PM, Naveen N Rao wrote: > On 2015/09/24 08:32AM, Stephane Eranian wrote: > > On Thu, Sep 24, 2015 at 5:57 AM, Jiri Olsa wrote: > > > > > > On Thu, Sep 24, 2015 at 05:41:58PM +0530, Naveen N. Rao wrote: > > > > perf build currently fails on powerpc: > > > > > >

Re: [PATCH v4 11/32] cxlflash: Refine host/device attributes

On 26/09/15 09:14, Matthew R. Ochs wrote: Implement the following suggestions and add two new attributes to allow for debugging the port LUN table. - use scnprintf() instead of snprintf() - use DEVICE_ATTR_RO and DEVICE_ATTR_RW Suggested-by: Shane Seymour

Re: [PATCH RFC 0/5] powerpc:numa Add serial nid support

On 28.09.2015 [13:44:42 +0300], Denis Kirjanov wrote: > On 9/27/15, Raghavendra K T wrote: > > Problem description: > > Powerpc has sparse node numbering, i.e. on a 4 node system nodes are > > numbered (possibly) as 0,1,16,17. At a lower level, we map the chipid

Re: [PATCH RFC 2/5] powerpc:numa Rename functions referring to nid as chipid

On 27.09.2015 [23:59:10 +0530], Raghavendra K T wrote: > There is no change in the fuctionality > > Signed-off-by: Raghavendra K T > --- > arch/powerpc/mm/numa.c | 42 +- > 1 file changed, 21 insertions(+), 21

Re: [PATCH RFC 4/5] powerpc:numa Add helper functions to maintain chipid to nid mapping

On 27.09.2015 [23:59:12 +0530], Raghavendra K T wrote: > Create arrays that maps serial nids and sparse chipids. > > Note: My original idea had only two arrays of chipid to nid map. Final > code is inspired by driver/acpi/numa.c that maps a proximity node with > a logical node by Takayoshi Kochi

Re: [PATCH RFC 0/5] powerpc:numa Add serial nid support

On 27.09.2015 [23:59:08 +0530], Raghavendra K T wrote: > Problem description: > Powerpc has sparse node numbering, i.e. on a 4 node system nodes are > numbered (possibly) as 0,1,16,17. At a lower level, we map the chipid > got from device tree is naturally mapped (directly) to nid. chipid is a

Re: [PATCH 00/31] powerpc/mm: Update page table format for book3s 64

On Mon, 2015-09-28 at 10:26 +0530, Aneesh Kumar K.V wrote: > Scott Wood writes: > > > On Tue, 2015-09-22 at 12:18 +0530, Aneesh Kumar K.V wrote: > > > Scott Wood writes: > > > > > > > On Mon, 2015-09-21 at 12:10 +0530, Aneesh Kumar K.V wrote: >

Re: [PATCH RFC 3/5] powerpc:numa create 1:1 mappaing between chipid and nid

On 27.09.2015 [23:59:11 +0530], Raghavendra K T wrote: > Once we have made the distinction between nid and chipid > create a 1:1 mapping between them. This makes compacting the > nids easy later. > > No functionality change. > > Signed-off-by: Raghavendra K T

Re: [PATCH RFC 3/5] powerpc:numa create 1:1 mappaing between chipid and nid

On 27.09.2015 [23:59:11 +0530], Raghavendra K T wrote: > Once we have made the distinction between nid and chipid > create a 1:1 mapping between them. This makes compacting the > nids easy later. Didn't the previous patch just do the opposite of... > @@ -286,7 +308,7 @@ int

Re: [PATCH v8 1/4] perf, kvm/{x86, s390}: Remove dependency on uapi/kvm_perf.h

Hemant Kumar writes: > Its better to remove the dependency on uapi/kvm_perf.h to allow dynamic > discovery of kvm events (if its needed). To do this, some extern > variables have been introduced with which we can keep the generic > functions generic. > > Signed-off-by:

Re: [PATCH v8 1/4] perf,kvm/{x86,s390}: Remove dependency on uapi/kvm_perf.h

On 9/28/15 7:00 AM, Alexander Yarygin wrote: diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index fc1cffb..ef25fcf 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -31,20 +31,18 @@ #include #ifdef HAVE_KVM_STAT_SUPPORT -#include #include

Re: [PATCH v8 1/4] perf,kvm/{x86,s390}: Remove dependency on uapi/kvm_perf.h

On 9/28/15 9:16 AM, Scott Wood wrote: On Mon, 2015-09-28 at 08:31 -0600, David Ahern wrote: On 9/28/15 7:00 AM, Alexander Yarygin wrote: diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index fc1cffb..ef25fcf 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c

Re: [PATCH v8 1/4] perf,kvm/{x86,s390}: Remove dependency on uapi/kvm_perf.h

On Mon, 2015-09-28 at 08:31 -0600, David Ahern wrote: > On 9/28/15 7:00 AM, Alexander Yarygin wrote: > > > diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c > > > index fc1cffb..ef25fcf 100644 > > > --- a/tools/perf/builtin-kvm.c > > > +++ b/tools/perf/builtin-kvm.c > > > @@ -31,20

Re: [PATCH v7 1/4] perf,kvm/{x86,s390}: Remove dependency on uapi/kvm_perf.h

Am 24.09.2015 um 21:02 schrieb Hemant Kumar: > Its better to remove the dependency on uapi/kvm_perf.h to allow dynamic > discovery of kvm events (if its needed). To do this, some extern > variables have been introduced with which we can keep the generic > functions generic. > > Signed-off-by:

Re: [PATCH v2 1/2] powerpc/selftest: Add gettimeofday() benchmark

On 9/28/15, Michael Neuling wrote: > On Fri, 2015-09-25 at 11:37 +0200, Gabriel Paubert wrote: >> On Fri, Sep 25, 2015 at 12:28:30PM +0300, Denis Kirjanov wrote: >> > On 9/25/15, Arnd Bergmann wrote: >> > > On Friday 25 September 2015 14:01:39 Michael Neuling

Re: [PATCH v2 1/2] powerpc/selftest: Add gettimeofday() benchmark

On Fri, 2015-09-25 at 11:37 +0200, Gabriel Paubert wrote: > On Fri, Sep 25, 2015 at 12:28:30PM +0300, Denis Kirjanov wrote: > > On 9/25/15, Arnd Bergmann wrote: > > > On Friday 25 September 2015 14:01:39 Michael Neuling wrote: > > >> This adds a benchmark directory to the powerpc

Re: [PATCH RFC 0/5] powerpc:numa Add serial nid support

On 9/27/15, Raghavendra K T wrote: > Problem description: > Powerpc has sparse node numbering, i.e. on a 4 node system nodes are > numbered (possibly) as 0,1,16,17. At a lower level, we map the chipid > got from device tree is naturally mapped (directly) to nid.

Re: [PATCH v4 08/32] cxlflash: Fix to avoid CXL services during EEH

Reviewed-by: Brian King -- Brian King Power Linux I/O IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

Re: [PATCH v4 07/32] cxlflash: Fix context encode mask width

-BEGIN PGP SIGNED MESSAGE- Hash: SHA512 Looks good to me. Reviewed-by: Daniel Axtens Regards, Daniel "Matthew R. Ochs" writes: > The context encode mask covers more than 32-bits, making it > a long integer. This should be noted by

Re: [PATCH v2 06/25] powerpc32: iounmap() cannot vunmap() area mapped by TLBCAMs either

On Tue, Sep 22, 2015 at 06:50:40PM +0200, Christophe Leroy wrote: > iounmap() cannot vunmap() area mapped by TLBCAMs either > > Signed-off-by: Christophe Leroy > --- > No change in v2 > > arch/powerpc/mm/pgtable_32.c | 4 +++- > 1 file changed, 3 insertions(+), 1

Re: [PATCH v2 01/25] powerpc/8xx: Save r3 all the time in DTLB miss handler

On Tue, Sep 22, 2015 at 06:50:29PM +0200, Christophe Leroy wrote: > We are spending between 40 and 160 cycles with a mean of 65 cycles in > the TLB handling routines (measured with mftbl) so make it more > simple althought it adds one instruction. > > Signed-off-by: Christophe Leroy

Re: [PATCH v4 09/32] cxlflash: Correct naming of limbo state and waitq

-BEGIN PGP SIGNED MESSAGE- Hash: SHA512 "Matthew R. Ochs" writes: Looks good from an EEH point of view: in an error situation, your driver asks to be reset and then is waiting for CXL and EEH to carry that out, so 'reset' matches with that as well.

Re: [PATCH v2 05/25] powerpc/8xx: Fix vaddr for IMMR early remap

On Tue, Sep 22, 2015 at 06:50:38PM +0200, Christophe Leroy wrote: > Memory: 124428K/131072K available (3748K kernel code, 188K rwdata, > 648K rodata, 508K init, 290K bss, 6644K reserved) > Kernel virtual memory layout: > * 0xfffdf000..0xf000 : fixmap > * 0xfde0..0xfe00 :

Re: [PATCH v2 07/25] powerpc32: refactor x_mapped_by_bats() and x_mapped_by_tlbcam() together

On Tue, Sep 22, 2015 at 06:50:42PM +0200, Christophe Leroy wrote: > x_mapped_by_bats() and x_mapped_by_tlbcam() serve the same kind of > purpose, so lets group them into a single function. > > Signed-off-by: Christophe Leroy > --- > No change in v2 > >

Re: [PATCH v4 06/32] cxlflash: Fix to avoid sizeof(bool)

-BEGIN PGP SIGNED MESSAGE- Hash: SHA512 Looks good to me. Reviewed-by: Daniel Axtens Regards, Daniel "Matthew R. Ochs" writes: > Using sizeof(bool) is considered poor form for various reasons and > sparse warns us of that. Correct by

Re: [PATCH v4 08/32] cxlflash: Fix to avoid CXL services during EEH

You have two versions of check_state() below, which is a bit confusing. It looks like you've moved the function and also added the up/down of the read semaphore. I assume that's all that changed? > > /** > + * check_state() - checks and responds to the current adapter state > + * @cfg:

Re: [PATCH v4 17/32] cxlflash: Remove dual port online dependency

-BEGIN PGP SIGNED MESSAGE- Hash: SHA512 Hi, > static int afu_set_wwpn(struct afu *afu, int port, u64 *fc_regs, u64 wwpn) > { > - int ret = 0; > + int rc = 0; I realise it's nice to have things consistent, but making this change now makes the rest of the patch quite difficult to

Re: [PATCH v4 32/32] cxlflash: Fix to avoid potential deadlock on EEH

On 09/25/2015 06:19 PM, Matthew R. Ochs wrote: > static int write_same16(struct scsi_device *sdev, > @@ -433,9 +451,20 @@ static int write_same16(struct scsi_device *sdev, > put_unaligned_be32(ws_limit < left ? ws_limit : left, > _cmd[10]); > > +

Re: [PATCH v2 08/25] powerpc/8xx: Map IMMR area with 512k page at a fixed address

On Tue, Sep 22, 2015 at 06:50:44PM +0200, Christophe Leroy wrote: > diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c > index 3fd9083..1f2fdbc 100644 > --- a/arch/powerpc/mm/pgtable_32.c > +++ b/arch/powerpc/mm/pgtable_32.c > @@ -49,6 +49,10 @@ EXPORT_SYMBOL(ioremap_bot);

Re: [PATCH v4 27/32] cxlflash: Fix to prevent stale AFU RRQ

-BEGIN PGP SIGNED MESSAGE- Hash: SHA512 "Matthew R. Ochs" writes: > Following an adapter reset, the AFU RRQ that resides in host memory > holds stale data. This can lead to a condition where the RRQ interrupt > handler tries to process stale entries and/or

Re: [PATCH v4 29/32] cxlflash: Fix to double the delay each time

-BEGIN PGP SIGNED MESSAGE- Hash: SHA512 "Matthew R. Ochs" writes: > From: Manoj Kumar > > The operator used to double the delay is incorrect and > does not result in delay doubling. > > To fix, use a left shift instead of the XOR

Re: [PATCH v4 24/32] cxlflash: Fix MMIO and endianness errors

On 26/09/15 09:18, Matthew R. Ochs wrote: Sparse uncovered several errors with MMIO operations (accessing directly) and handling endianness. These can cause issues when running in different environments. Introduce __iomem and proper endianness tags/swaps where appropriate to make driver sparse

[PATCH v11 1/6] genalloc:support memory-allocation with bytes-alignment to genalloc

Bytes alignment is required to manage some special RAM, so add gen_pool_first_fit_align to genalloc, meanwhile add gen_pool_alloc_data to pass data to gen_pool_first_fit_align(modify gen_pool_alloc as a wrapper) Signed-off-by: Zhao Qiang --- Changes for v6: -

[PATCH v11 2/6] genalloc:support allocating specific region

Add new algo for genalloc, it reserve a specific region of memory matching the size requirement (no alignment constraint) Signed-off-by: Zhao Qiang --- Changes for v9: - reserve a specific region, if the return region - is not during the specific region,

[PATCH v11 3/6] CPM/QE: use genalloc to manage CPM/QE muram

Use genalloc to manage CPM/QE muram instead of rheap. Signed-off-by: Zhao Qiang --- Changes for v9: - splitted from patch 3/5, modify cpm muram management functions. Changes for v10: - modify cpm muram first, then move to qe_common - modify

[PATCH v11 4/6] QE/CPM: move muram management functions to qe_common

QE and CPM have the same muram, they use the same management functions. Now QE support both ARM and PowerPC, it is necessary to move QE to "driver/soc", so move the muram management functions from cpm_common to qe_common for preparing to move QE code to "driver/soc" Signed-off-by: Zhao Qiang

[PATCH v11 5/6] QE: use subsys_initcall to init qe

Use subsys_initcall to init qe to adapt ARM architecture. Remove qe_reset from PowerPC platform file. Signed-off-by: Zhao Qiang --- arch/powerpc/platforms/83xx/km83xx.c | 2 -- arch/powerpc/platforms/83xx/mpc832x_mds.c | 2 --

[PATCH v11 6/6] QE: Move QE from arch/powerpc to drivers/soc

ls1 has qe and ls1 has arm cpu. move qe from arch/powerpc to drivers/soc/fsl to adapt to powerpc and arm Signed-off-by: Zhao Qiang --- Changes for v2: - move code to driver/soc Changes for v3: - change drivers/soc/qe to drivers/soc/fsl-qe Changes for v4:

Re: [PATCH v2 11/25] powerpc/8xx: map 16M RAM at startup

On Tue, Sep 22, 2015 at 06:50:50PM +0200, Christophe Leroy wrote: > On recent kernels, with some debug options like for instance > CONFIG_LOCKDEP, the BSS requires more than 8M memory, allthough > the kernel code fits in the first 8M. > Today, it is necessary to activate CONFIG_PIN_TLB to get more

Re: [PATCH 00/31] powerpc/mm: Update page table format for book3s 64

On Mon, 2015-09-28 at 10:26 +0530, Aneesh Kumar K.V wrote: > > In any case, "nohash" is the term used elsewhere. > > How about using swtlb ? (nohash always confused me, It would be nice > to be explict and us software tlb ?) Stick to nohash, that's been our convention so far, I don't see the

Re: [PATCH v2 20/25] powerpc32: Remove clear_pages() and define clear_page() inline

On Tue, Sep 22, 2015 at 06:51:09PM +0200, Christophe Leroy wrote: > clear_pages() is never used, and PPC32 is the only architecture > (still) having this function. Neither PPC64 nor any other > architecture has it. It is used, by clear_page(). > This patch removes clear_page() and move

Re: [PATCH v2 22/25] powerpc32: move xxxxx_dcache_range() functions inline

On Tue, Sep 22, 2015 at 06:51:13PM +0200, Christophe Leroy wrote: > flush/clean/invalidate _dcache_range() functions are all very > similar and are quite short. They are mainly used in __dma_sync() > perf_event locate them in the top 3 consumming functions during > heavy ethernet activity > >

Re: [PATCH v2 14/25] powerpc32: remove ioremap_base

On Tue, Sep 22, 2015 at 06:50:56PM +0200, Christophe Leroy wrote: > ioremap_base is not initialised and is nowhere used so remove it > > Signed-off-by: Christophe Leroy > --- > No change in v2 Could you also clean up the references to ioremap_base in the comments?

[PATCH v17 00/19] perf, tools: Add support for PMU events in JSON format

CPUs support a large number of performance monitoring events (PMU events) and often these events are very specific to an architecture/model of the CPU. To use most of these PMU events with perf, we currently have to identify them by their raw codes: perf stat -e r100f2 sleep 1 This

[PATCH v17 02/19] perf, tools, jevents: Program to convert JSON file to C style file

From: Andi Kleen This is a modified version of an earlier patch by Andi Kleen. We expect architectures to describe the performance monitoring events for each CPU in a corresponding JSON file, which look like: [ { "EventCode": "0x00",

[PATCH v17 05/19] perf, tools: Support CPU id matching for x86 v2

From: Andi Kleen Implement the code to match CPU types to mapfile types for x86 based on CPUID. This extends an existing similar function, but changes it to use the x86 mapfile cpu description. This allows to resolve event lists generated by jevents. Signed-off-by: Andi

[PATCH v17 06/19] perf, tools: Support alias descriptions

From: Andi Kleen Add support to print alias descriptions in perf list, which are taken from the generated event files. The sorting code is changed to put the events with descriptions at the end. The descriptions are printed as possibly multiple word wrapped lines. Example

[PATCH v17 08/19] perf, tools: Add a --no-desc flag to perf list

From: Andi Kleen Add a --no-desc flag to perf list to not print the event descriptions that were earlier added for JSON events. This may be useful to get a less crowded listing. It's still default to print descriptions as that is the more useful default for most users.

[PATCH v17 15/19] perf, tools: Handle header line in mapfile

From: Andi Kleen To work with existing mapfiles, assume that the first line in 'mapfile.csv' is a header line and skip over it. Signed-off-by: Andi Kleen Signed-off-by: Sukadev Bhattiprolu Acked-by: Jiri Olsa

[PATCH v17 16/19] perf, tools: Add README for info on parsing JSON/map files

Signed-off-by: Sukadev Bhattiprolu Acked-by: Jiri Olsa --- tools/perf/pmu-events/README | 122 +++ 1 file changed, 122 insertions(+) create mode 100644 tools/perf/pmu-events/README diff --git

[PATCH v17 18/19] perf, tools, pmu-events: Fix fixed counters on Intel

From: Andi Kleen The JSON event lists use a different encoding for fixed counters than perf for instructions and cycles (ref-cycles is ok) This lead to some common events like inst_retired.any or cpu_clk_unhalted.thread not counting, when specified with their JSON name.

Re: [PATCH v4 30/32] cxlflash: Fix to avoid corrupting adapter fops

On 26/09/15 09:19, Matthew R. Ochs wrote: The fops owned by the adapter can be corrupted in certain scenarios, opening a window where certain fops are temporarily NULLed before being reset to their proper value. This can potentially lead software to make incorrect decisions, leaving the user

Re: [PATCH v4 26/32] cxlflash: Correct spelling, grammar, and alignment mistakes

On 26/09/15 09:18, Matthew R. Ochs wrote: There are several spelling and grammar mistakes throughout the driver. Additionally there are a handful of places where there are extra lines and unnecessary variables/statements. These are a nuisance and pollute the driver. Fix spelling and grammar

Re: [PATCH v4 31/32] cxlflash: Correct trace string

On 26/09/15 09:19, Matthew R. Ochs wrote: The trace following the failure of alloc_mem() incorrectly identifies which function failed. This can lead to misdiagnosing a failure. Fix the string to correctly indicate that alloc_mem() failed. Reported-by: Brian King

Re: [PATCH v4 25/32] cxlflash: Fix to prevent EEH recovery failure

-BEGIN PGP SIGNED MESSAGE- Hash: SHA512 "Matthew R. Ochs" writes: > The process_sense() routine can perform a read capacity which > can take some time to complete. If an EEH occurs while waiting > on the read capacity, the EEH handler is unable to obtain the

Re: [PATCH v2 13/25] powerpc/8xx: also use r3 in the ITLB miss in all situations

On Tue, Sep 22, 2015 at 06:50:54PM +0200, Christophe Leroy wrote: > We are spending between 40 and 160 cycles with a mean of 65 cycles > in the TLB handling routines (measured with mftbl) so make it more > simple althought it adds one instruction > > Signed-off-by: Christophe Leroy

Re: [PATCH v2 15/25] powerpc/8xx: move 8xx SPRN defines into reg_8xx.h and add some missing ones

On Tue, Sep 22, 2015 at 06:50:58PM +0200, Christophe Leroy wrote: > Move 8xx SPRN defines into reg_8xx.h and add some missing ones > > Signed-off-by: Christophe Leroy > --- > No change in v2 Why are they being moved? Why are they being separated from the bit

Re: [PATCH v2 21/25] powerpc: add inline functions for cache related instructions

On Tue, Sep 22, 2015 at 06:51:11PM +0200, Christophe Leroy wrote: > This patch adds inline functions to use dcbz, dcbi, dcbf, dcbst > from C functions > > Signed-off-by: Christophe Leroy > --- > New in v2 > > arch/powerpc/include/asm/cache.h | 19 +++ >

[PATCH v17 01/19] perf, tools: Add jsmn `jasmine' JSON parser

From: Andi Kleen I need a JSON parser. This adds the simplest JSON parser I could find -- Serge Zaitsev's jsmn `jasmine' -- to the perf library. I merely converted it to (mostly) Linux style and added support for non 0 terminated input. The parser is quite straight forward

[PATCH v17 03/19] perf, tools: Use pmu_events table to create aliases

At run time (when 'perf' is starting up), locate the specific table of PMU events that corresponds to the current CPU. Using that table, create aliases for the each of the PMU events in the CPU. The use these aliases to parse the user specified perf event. In short this would allow the user to

[PATCH v17 04/19] perf, tools: Support CPU ID matching for Powerpc

Implement code that returns the generic CPU ID string for Powerpc. This will be used to identify the specific table of PMU events to parse/compare user specified events against. Signed-off-by: Sukadev Bhattiprolu Acked-by: Jiri Olsa ---

[PATCH v17 07/19] perf, tools: Query terminal width and use in perf list

From: Andi Kleen Automatically adapt the now wider and word wrapped perf list output to wider terminals. This requires querying the terminal before the auto pager takes over, and exporting this information from the pager subsystem. Signed-off-by: Andi Kleen

[PATCH v17 10/19] perf, tools, jevents: Add support for long descriptions

Implement support in jevents to parse long descriptions for events that may have them in the JSON files. A follow on patch will make this long description available to user through the 'perf list' command. Signed-off-by: Andi Kleen Signed-off-by: Sukadev Bhattiprolu

[PATCH v17 09/19] perf, tools: Add override support for event list CPUID

From: Andi Kleen Add a PERF_CPUID variable to override the CPUID of the current CPU (within the current architecture). This is useful for testing, so that all event lists can be tested on a single system. Signed-off-by: Andi Kleen Signed-off-by:

[PATCH v17 13/19] perf, tools, jevents: Add support for event topics

Allow assigning categories "Topics" field to the PMU events i.e. process the topic field from the JSON file and add a corresponding topic field to the generated C events tables. Signed-off-by: Andi Kleen Signed-off-by: Sukadev Bhattiprolu

[PATCH v17 11/19] perf, tools: Add alias support for long descriptions

Previously we were dropping the useful longer descriptions that some events have in the event list completely. Now that jevents provides support for longer descriptions (see previous patch), add support for parsing the long descriptions Signed-off-by: Andi Kleen

[PATCH v17 14/19] perf, tools: Add support for event list topics

From: Andi Kleen Add support to group the output of perf list by the Topic field in the JSON file. Example output: % perf list ... Cache: l1d.replacement [L1D data line replacements] l1d_pend_miss.pending [L1D miss oustandings duration in cycles]

[PATCH v17 12/19] perf, tools: Support long descriptions with perf list

Previously we were dropping the useful longer descriptions that some events have in the event list completely. This patch makes them appear with perf list. Old perf list: baclears: baclears.all [Counts the number of baclears] vs new: perf list -v: ... baclears: baclears.all

[PATCH v17 17/19] perf, tools: Make alias matching case-insensitive

From: Andi Kleen Make alias matching the events parser case-insensitive. This is useful with the JSON events. perf uses lower case events, but the CPU manuals generally use upper case event names. The JSON files use lower case by default too. But if we search case

[PATCH v17 19/19] perf, tools, pmu-events: Add Skylake frontend MSR support

From: Andi Kleen Add support for the "frontend" extra MSR on Skylake in the JSON conversion. Signed-off-by: Andi Kleen --- tools/perf/pmu-events/jevents.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/perf/pmu-events/jevents.c

Re: [PATCH v3 3/3] dmaengine: mpc512x: initialize with subsys_initcall()

On 25.09.2015 03:16, Timur Tabi wrote: > Alexander Popov wrote: >> Initialize Freescale MPC512x DMA driver with subsys_initcall() >> to allow the depending drivers to call dma_request_slave_channel() >> during their probe. >> >> Signed-off-by: Alexander Popov > > Is there

Re: [PATCH v3 2/3] powerpc/512x: add a device tree binding for LocalPlus Bus FIFO

On 25.09.2015 03:18, Timur Tabi wrote: > Alexander Popov wrote: >> +- dma-names: should be "rx-tx"; > > Why bother, if it can only be one value? I've just followed devicetree/bindings/dma/dma.txt... This "rx-tx" doesn't mean much but it could show that LocalPlus Bus FIFO uses a single DMA

Re: [PATCH v3 2/3] powerpc/512x: add a device tree binding for LocalPlus Bus FIFO

Alexander Popov wrote: I've just followed devicetree/bindings/dma/dma.txt... This "rx-tx" doesn't mean much but it could show that LocalPlus Bus FIFO uses a single DMA read-write channel. Should I really drop it? Hmmm, I'm not sure. Is there anything else (besides your driver) that parses

Re: [PATCH v3 1/3] powerpc/512x: add LocalPlus Bus FIFO device driver

Hello, Timur, thanks a lot for your review. I'll fix all the issues you pointed at and return with v4. The only question I have: why calling dma_unmap_single() from within a spinlock is a bad practice? Best regards, Alexander ___ Linuxppc-dev mailing

Re: [PATCH v3 1/3] powerpc/512x: add LocalPlus Bus FIFO device driver

Alexander Popov wrote: The only question I have: why calling dma_unmap_single() from within a spinlock is a bad practice? I don't know, but usually functions that allocate or free memory cannot be called from within a spinlock. You need to check that. Since the MPC5121 is a single-core