Re: [PATCH 19/31] powerpc/mm: Convert 4k hash insert to C

Benjamin Herrenschmidt writes: > On Mon, 2015-09-21 at 12:10 +0530, Aneesh Kumar K.V wrote: >> Signed-off-by: Aneesh Kumar K.V >> --- >> arch/powerpc/mm/Makefile| 3 + >> arch/powerpc/mm/hash64_64k.c| 204

Re: [PATCH] perf record: Limit --intr-regs to platforms supporting PERF_REGS

On 2015/09/29 08:53AM, Jiri Olsa wrote: > On Tue, Sep 29, 2015 at 11:06:17AM +0530, Naveen N. Rao wrote: > > On 2015/09/24 10:15PM, Naveen N Rao wrote: > > > On 2015/09/24 08:32AM, Stephane Eranian wrote: > > > > On Thu, Sep 24, 2015 at 5:57 AM, Jiri Olsa wrote: > > > > > > > >

Re: [PATCH] perf record: Limit --intr-regs to platforms supporting PERF_REGS

On Tue, Sep 29, 2015 at 11:06:17AM +0530, Naveen N. Rao wrote: > On 2015/09/24 10:15PM, Naveen N Rao wrote: > > On 2015/09/24 08:32AM, Stephane Eranian wrote: > > > On Thu, Sep 24, 2015 at 5:57 AM, Jiri Olsa wrote: > > > > > > > > On Thu, Sep 24, 2015 at 05:41:58PM +0530, Naveen

Re: [PATCH v3 2/3] powerpc/512x: add a device tree binding for LocalPlus Bus FIFO

On 28.09.2015 16:26, Timur Tabi wrote: > Alexander Popov wrote: >> I've just followed devicetree/bindings/dma/dma.txt... >> This "rx-tx" doesn't mean much but it could show that LocalPlus Bus FIFO >> uses a single DMA read-write channel. Should I really drop it? > > Hmmm, I'm not sure. Is there

Re: [PATCH v3 1/3] powerpc/512x: add LocalPlus Bus FIFO device driver

On 28.09.2015 16:18, Timur Tabi wrote: > Alexander Popov wrote: >> The only question I have: why calling dma_unmap_single() from within >> a spinlock is a bad practice? > > I don't know, but usually functions that allocate or free memory cannot be > called from within a spinlock. You need to

[PATCH] powerpc/configs: Re-enable CONFIG_SCSI_DH

Commit 086b91d052eb ("scsi_dh: integrate into the core SCSI code") changed CONFIG_SCSI_DH from tristate to bool. Our defconfigs have CONFIG_SCSI_DH=m, which the kconfig machinery warns us is invalid, but instead of converting it to =y it leaves it unset. This means we loose the CONFIG_SCSI_DH

Re: [PATCH] perf record: Limit --intr-regs to platforms supporting PERF_REGS

On Tue, Sep 29, 2015 at 01:30:10PM +0530, Naveen N. Rao wrote: SNIP > > > Suka has also posted a fix for this with a different approach [1]. Can > > > you please ack/pull one of these versions? Building perf is broken on > > > v4.3-rc due to this. > > > > I did not get any answer for

Re: [PATCH v4 30/32] cxlflash: Fix to avoid corrupting adapter fops

"Matthew R. Ochs" writes: > The corruption that this fix remedies is due to the fact that the fops > is initially defaulted to values found within a static structure. When > the fops is handed down to the CXL services later in the attach path, > certain services are

Re: [PATCH v4 32/32] cxlflash: Fix to avoid potential deadlock on EEH

"Matthew R. Ochs" writes: > Ioctl threads that use scsi_execute() can run for an excessive amount > of time due to the fact that they have lengthy timeouts and retry logic > built in. Under normal operation this is not an issue. However, once EEH > enters the picture,

Re: [PATCH v4 29/32] cxlflash: Fix to double the delay each time

> On Sep 28, 2015, at 8:40 PM, Daniel Axtens wrote: > > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA512 > > "Matthew R. Ochs" writes: > >> From: Manoj Kumar >> >> The operator used to double the delay is incorrect and

Re: [PATCH v4 12/32] cxlflash: Fix to avoid spamming the kernel log

> On Sep 29, 2015, at 12:05 AM, Andrew Donnellan > wrote: > On 26/09/15 09:15, Matthew R. Ochs wrote: >> During run-time the driver can be very chatty and spam the system >> kernel log. Various print statements can be limited and/or moved >> to development-only

Re: [PATCH] perf record: Limit --intr-regs to platforms supporting PERF_REGS

On Tue, Sep 29, 2015 at 11:10:02AM -0700, Sukadev Bhattiprolu wrote: SNIP > > diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c > index 885e8ac..6b8eb13 100644 > --- a/tools/perf/util/perf_regs.c > +++ b/tools/perf/util/perf_regs.c > @@ -6,6 +6,7 @@ const struct sample_reg

Re: [PATCH v4 23/32] cxlflash: Fix function prolog parameters and return codes

> On Sep 28, 2015, at 11:36 PM, Andrew Donnellan > wrote: > On 26/09/15 09:18, Matthew R. Ochs wrote: >> >> */ >> static int send_tmf(struct afu *afu, struct scsi_cmnd *scp, u64 tmfcmd) >> { >> @@ -491,9 +490,7 @@ static const char *cxlflash_driver_info(struct

Re: [PATCH v4 29/32] cxlflash: Fix to double the delay each time

"Matthew R. Ochs" writes: >> On Sep 28, 2015, at 8:40 PM, Daniel Axtens wrote: >> >> -BEGIN PGP SIGNED MESSAGE- >> Hash: SHA512 >> >> "Matthew R. Ochs" writes: >> >>> From: Manoj Kumar

Re: [PATCH 00/31] powerpc/mm: Update page table format for book3s 64

On Mon, 2015-09-28 at 11:41 -0500, Scott Wood wrote: > On Mon, 2015-09-28 at 10:26 +0530, Aneesh Kumar K.V wrote: > > Scott Wood writes: > > > > > > In any case, "nohash" is the term used elsewhere. > > > > How about using swtlb ? (nohash always confused me, It would be

[PATCH V2 01/31] powerpc/mm: move pte headers to book3s directory

Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/{pte-hash32.h => book3s/32/hash.h} | 0 arch/powerpc/include/asm/{pte-hash64.h => book3s/64/hash.h} | 0 arch/powerpc/include/asm/pgtable-ppc32.h| 2 +-

[PATCH V2 06/31] powerpc/mm: Delete booke bits from book3s

We also move __ASSEMBLY__ towards the end of header. This avoid having #ifndef __ASSEMBLY___ all over the header Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/32/pgtable.h | 93 +++-

[PATCH V2 07/31] powerpc/mm: Don't have generic headers introduce functions touching pte bits

We are going to drop pte_common.h in the later patch. The idea is to enable hash code not require to define all PTE bits. Having PTE bits defined in pte_common.h made the code unnecessarily complex. Signed-off-by: Aneesh Kumar K.V ---

[PATCH V2 05/31] powerpc/mm: Move hash specific pte width and other defines to book3s

This further make a copy of pte defines to book3s/64/hash*.h. This remove the dependency on ppc64-4k.h and ppc64-64k.h Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/hash-4k.h | 87 ++-

[PATCH V2 24/31] powerpc/mm: Convert __hash_page_64K to C

Convert from asm to C Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/hash-64k.h | 3 +- arch/powerpc/include/asm/book3s/64/hash.h | 1 + arch/powerpc/mm/hash64_64k.c | 134 +++-

[PATCH V2 10/31] powerpc/mm: Don't use pmd_val, pud_val and pgd_val as lvalue

We convert them static inline function here as we did with pte_val in the previous patch Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/32/pgtable.h | 6 - arch/powerpc/include/asm/book3s/64/hash-4k.h | 6 -

[PATCH V2 09/31] powerpc/mm: Don't use pte_val as lvalue

We also convert few #define to static inline in this patch for better type checking Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/pgtable.h | 112 -- arch/powerpc/include/asm/page.h | 10 ++-

[PATCH V2 25/31] powerpc/mm: Convert 4k insert from asm to C

This is similar to 64K insert. May be we want to consolidate Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/mm/Makefile| 6 +- arch/powerpc/mm/hash64_4k.c | 139 + arch/powerpc/mm/hash_low_64.S | 331

[PATCH V2 11/31] powerpc/mm: Move hash64 PTE bits from book3s/64/pgtable.h to hash.h

This enables us to keep hash64 related bits together, and makes it easy to follow. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/hash.h| 442 ++- arch/powerpc/include/asm/book3s/64/pgtable.h | 441

[PATCH V2 12/31] powerpc/mm: Move PTE bits from generic functions to hash64 functions.

functions which operate on pte bits are moved to hash*.h and other generic functions are moved to pgtable.h Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/32/pgtable.h | 177 arch/powerpc/include/asm/book3s/64/hash.h

[PATCH 1/3] cxl: fix leak of IRQ names in cxl_free_afu_irqs()

cxl_free_afu_irqs() doesn't free IRQ names when it releases an AFU's IRQ ranges. The userspace API equivalent in afu_release_irqs() calls afu_irq_name_free() to release the IRQ names. Call afu_irq_name_free() in cxl_free_afu_irqs() to release the IRQ names. Make afu_irq_name_free() non-static to

[PATCH V2 04/31] powerpc/mm: make a separate copy for book3s (part 2)

Keep it seperate to make rebasing easier Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/32/pgtable.h | 4 ++-- arch/powerpc/include/asm/book3s/64/pgtable.h | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git

[PATCH V2 14/31] powerpc/booke: Move booke headers (part 2)

Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/{pgtable-ppc32.h => nohash/32/pgtable.h} | 0 arch/powerpc/include/asm/{pgtable-ppc64.h => nohash/64/pgtable.h} | 2 +- arch/powerpc/include/asm/nohash/pgtable.h | 8 3

[PATCH V2 13/31] powerpc/booke: Move booke headers (part 1)

Move the booke related headers below booke/32 or booke/64 We are splitting this change into multiple patch to make the rebasing easier. The following patches can be folded into this if needed. They are kept separate for easier review. Signed-off-by: Aneesh Kumar K.V

[PATCH V2 28/31] powerpc/mm: Move WIMG update to helper.

Only difference here is, we apply the WIMG mapping early, so rflags passed to updatepp will also be changed. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/mm/hash64_4k.c | 5 - arch/powerpc/mm/hash64_64k.c | 10 --

[PATCH V2 29/31] powerpc/mm: Move hugetlb related headers

W.r.t hugetlb, we support two format for pmd. With book3s_64 and 64K linux page size, we can have pte at the pmd level. Hence we don't need to support hugepd there. For everything else hugepd is supported and pmd_huge is (0). Signed-off-by: Aneesh Kumar K.V ---

[PATCH 2/3] cxl: fix leak of ctx->irq_bitmap when releasing context via kernel API

At present, ctx->irq_bitmap is freed in afu_release_irqs(), which is called from afu_release() via cxl_context_detach(). Move the freeing of ctx->irq_bitmap from afu_release_irqs() to reclaim_ctx() (called through cxl_context_free()) so it's freed when releasing a context via the kernel API

[PATCH V2 00/31] powerpc/mm: Update page table format for book3s 64

Hi All, This patch series attempt to update book3s 64 linux page table format to make it more flexible. Our current pte format is very restrictive and we overload multiple pte bits. This is due to the non-availability of free bits in pte_t. We use pte_t to track the validity of 4K subpages. This

[PATCH V2 16/31] powerpc/booke: Move booke headers (part 4)

Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/nohash/32/pgtable.h | 16 arch/powerpc/include/asm/{ => nohash/32}/pte-40x.h | 0 arch/powerpc/include/asm/{ => nohash/32}/pte-44x.h | 0

[PATCH V2 15/31] powerpc/booke: Move booke headers (part 3)

Signed-off-by: Aneesh Kumar K.V --- .../include/asm/{pgtable-ppc64-4k.h => nohash/64/pgtable-4k.h} | 0 .../asm/{pgtable-ppc64-64k.h => nohash/64/pgtable-64k.h} | 0 arch/powerpc/include/asm/nohash/64/pgtable.h | 10 +- 3 files

[PATCH V2 22/31] powerpc/mm: Don't track subpage valid bit in pte_t

This free up 11 bits in pte_t. In the later patch we also change the pte_t format so that we can start supporting migration pte at pmd level. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/hash-4k.h | 10 +

[PATCH V2 23/31] powerpc/mm: Increase the width of #define

No real change, only style changes Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/hash.h | 26 +- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/powerpc/include/asm/book3s/64/hash.h

[PATCH V2 30/31] powerpc/mm: Move THP headers around

We support THP only with book3s_64 and 64K page size. Move THP details to hash64-64k.h to clarify the same. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/hash-64k.h | 126 + arch/powerpc/include/asm/book3s/64/hash.h | 223

[PATCH V2 31/31] powerpc/mm: Add a _PAGE_PTE bit

For a pte entry we will have _PAGE_PTE set. Our pte page address have a minimum alignment requirement of HUGEPD_SHIFT_MASK + 1. We use the lower 7 bits to indicate hugepd. ie. For pmd and pgd we can find: 1) _PAGE_PTE set pte -> indicate PTE 2) bits [2..6] non zero -> indicate hugepd. They

[PATCH 3/3] cxl: fix leak of ctx->mapping when releasing kernel API contexts

When a context is created via the kernel API, ctx->mapping is allocated within the kernel and thus needs to be freed when the context is freed. reclaim_ctx() attempts to do this for contexts with the ctx->kernelapi flag set, but afu_release() (which can be called from the kernel API through

[PATCH V2 03/31] powerpc/mm: make a separate copy for book3s

In this patch we do: cp pgtable-ppc32.h book3s/32/pgtable.h cp pgtable-ppc64.h book3s/64/pgtable.h This enable us to do further changes to hash specific config. We will change the page table format for 64bit hash in later patches. Signed-off-by: Aneesh Kumar K.V

[PATCH V2 02/31] powerpc/mm: move pte headers to book3s directory (part 2)

Splitting this so that rename can track changes to file. Before merging we will fold this Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/32/hash.h | 6 +++--- .../include/asm/{pte-hash64-4k.h => book3s/64/hash-4k.h}

[PATCH V2 18/31] powerpc/mm: Increase the pte frag size.

We will use the increased size to store more information of 4K pte when using 64K page size. The idea is to free up bits in pte_t. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/pgalloc-64.h | 12 ++-- 1 file changed, 6 insertions(+), 6

[PATCH V2 17/31] powerpc/booke: Move booke headers (part 5)

Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/nohash/32/pte-40x.h | 6 +++--- arch/powerpc/include/asm/nohash/32/pte-44x.h | 6 +++--- arch/powerpc/include/asm/nohash/32/pte-8xx.h | 6 +++---

[PATCH V2 27/31] powerpc/mm: Add helper for converting pte bit to hpte bits

Instead of open coding it in multiple code paths, export the helper and add more documentation. Also make sure we don't make assumption regarding pte bit position Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/hash.h | 1 +

[PATCH V2 08/31] powerpc/mm: Drop pte-common.h from BOOK3S 64

We copy only needed PTE bits define from pte-common.h to respective hash related header. This should greatly simply later patches in which we are going to change the pte format for hash config Signed-off-by: Aneesh Kumar K.V ---

[PATCH V2 19/31] powerpc/mm: Convert 4k hash insert to C

Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/mm/Makefile| 3 + arch/powerpc/mm/hash64_64k.c| 202 + arch/powerpc/mm/hash_low_64.S | 380 arch/powerpc/mm/hash_utils_64.c | 4 +- 4

[PATCH V2 21/31] powerpc/mm: make pte page hash index slot 8 bits

Currently we use 4 bits for each slot and pack all the 16 slot information related to a 64K linux page in a 64bit value. To do this we use 16 bits of pte_t. Move the hash slot valid bit out of pte_t and place them in the second half of pte page. We also use 8 bit per each slot. Signed-off-by:

[PATCH V2 20/31] powerpc/mm: update __real_pte to take address as argument

We will use this in the later patch to compute the right hash index Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/hash-64k.h | 2 +- arch/powerpc/include/asm/book3s/64/pgtable.h | 4 ++-- arch/powerpc/include/asm/nohash/64/pgtable.h |

[PATCH V2 26/31] powerpc/mm: Remove the dependency on pte bit position in asm code

We should not expect pte bit position in asm code. Simply by moving part of that to C Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/kernel/exceptions-64s.S | 16 +++- arch/powerpc/mm/hash_utils_64.c | 29 + 2 files

Re: [PATCH] perf record: Limit --intr-regs to platforms supporting PERF_REGS

On Tue, Sep 29, 2015 at 10:01:36PM +0530, Naveen N. Rao wrote: > On 2015/09/29 12:47PM, Jiri Olsa wrote: > > On Tue, Sep 29, 2015 at 01:30:10PM +0530, Naveen N. Rao wrote: > > > > SNIP > > > > > > > Suka has also posted a fix for this with a different approach [1]. > > > > > Can > > > > > you

Re: [PATCH RFC 0/5] powerpc:numa Add serial nid support

On 09/28/2015 10:34 PM, Nishanth Aravamudan wrote: On 28.09.2015 [13:44:42 +0300], Denis Kirjanov wrote: On 9/27/15, Raghavendra K T wrote: Problem description: Powerpc has sparse node numbering, i.e. on a 4 node system nodes are numbered (possibly) as

Re: [PATCH RFC 2/5] powerpc:numa Rename functions referring to nid as chipid

On 09/28/2015 10:57 PM, Nishanth Aravamudan wrote: On 27.09.2015 [23:59:10 +0530], Raghavendra K T wrote: There is no change in the fuctionality Signed-off-by: Raghavendra K T --- arch/powerpc/mm/numa.c | 42 +- 1

Re: [PATCH] perf record: Limit --intr-regs to platforms supporting PERF_REGS

On 2015/09/29 12:47PM, Jiri Olsa wrote: > On Tue, Sep 29, 2015 at 01:30:10PM +0530, Naveen N. Rao wrote: > > SNIP > > > > > Suka has also posted a fix for this with a different approach [1]. Can > > > > you please ack/pull one of these versions? Building perf is broken on > > > > v4.3-rc due

Re: [PATCH RFC 3/5] powerpc:numa create 1:1 mappaing between chipid and nid

On 09/28/2015 10:58 PM, Nishanth Aravamudan wrote: On 27.09.2015 [23:59:11 +0530], Raghavendra K T wrote: Once we have made the distinction between nid and chipid create a 1:1 mapping between them. This makes compacting the nids easy later. Didn't the previous patch just do the opposite

Re: [PATCH RFC 0/5] powerpc:numa Add serial nid support

On 09/28/2015 11:04 PM, Nishanth Aravamudan wrote: On 27.09.2015 [23:59:08 +0530], Raghavendra K T wrote: [...] 2) Map the sparse chipid got from device tree to a serial nid at kernel level (The idea proposed in this series). Pro: It is more natural to handle at kernel level than at lower

Re: [PATCH RFC 3/5] powerpc:numa create 1:1 mappaing between chipid and nid

On 09/28/2015 11:05 PM, Nishanth Aravamudan wrote: On 27.09.2015 [23:59:11 +0530], Raghavendra K T wrote: Once we have made the distinction between nid and chipid create a 1:1 mapping between them. This makes compacting the nids easy later. No functionality change. Signed-off-by: Raghavendra

Re: [PATCH v4 08/32] cxlflash: Fix to avoid CXL services during EEH

> On Sep 28, 2015, at 6:05 PM, Daniel Axtens wrote: > > You have two versions of check_state() below, which is a bit > confusing. It looks like you've moved the function and also added the > up/down of the read semaphore. I assume that's all that changed? Correct. It was

Re: [PATCH RFC 4/5] powerpc:numa Add helper functions to maintain chipid to nid mapping

On 09/28/2015 11:02 PM, Nishanth Aravamudan wrote: On 27.09.2015 [23:59:12 +0530], Raghavendra K T wrote: Create arrays that maps serial nids and sparse chipids. Note: My original idea had only two arrays of chipid to nid map. Final code is inspired by driver/acpi/numa.c that maps a proximity

Re: [PATCH v4 32/32] cxlflash: Fix to avoid potential deadlock on EEH

> On Sep 28, 2015, at 6:41 PM, Brian King wrote: > On 09/25/2015 06:19 PM, Matthew R. Ochs wrote: >> static int write_same16(struct scsi_device *sdev, >> @@ -433,9 +451,20 @@ static int write_same16(struct scsi_device *sdev, >> put_unaligned_be32(ws_limit <

Re: [PATCH] perf record: Limit --intr-regs to platforms supporting PERF_REGS

Jiri Olsa [jo...@redhat.com] wrote: | > I just tried it, but it fails. As Suka points out in his patch: | > "Adding perf_regs.o to util/Build unconditionally, exposes a | > redefinition error for 'perf_reg_value()' function (due to the static | > inline version in util/perf_regs.h). So use

Re: [PATCH v4 27/32] cxlflash: Fix to prevent stale AFU RRQ

> On Sep 28, 2015, at 8:36 PM, Daniel Axtens wrote: > > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA512 > > "Matthew R. Ochs" writes: > >> Following an adapter reset, the AFU RRQ that resides in host memory >> holds stale data. This can lead to a

Re: [PATCH v4 17/32] cxlflash: Remove dual port online dependency

> On Sep 28, 2015, at 6:37 PM, Daniel Axtens wrote: > > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA512 > > Hi, > >> static int afu_set_wwpn(struct afu *afu, int port, u64 *fc_regs, u64 wwpn) >> { >> -int ret = 0; >> +int rc = 0; > I realise it's nice to have things

Re: [PATCH RFC 0/5] powerpc:numa Add serial nid support

On 9/29/15, Raghavendra K T wrote: > On 09/28/2015 10:34 PM, Nishanth Aravamudan wrote: >> On 28.09.2015 [13:44:42 +0300], Denis Kirjanov wrote: >>> On 9/27/15, Raghavendra K T wrote: Problem description: Powerpc has

Re: [PATCH v4 25/32] cxlflash: Fix to prevent EEH recovery failure

> On Sep 28, 2015, at 8:25 PM, Daniel Axtens wrote: > > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA512 > > "Matthew R. Ochs" writes: > > >> The process_sense() routine can perform a read capacity which >> can take some time to complete. If an