Re: powerpc: Simplify module TOC handling

On Mon, 2016-18-01 at 00:44:27 UTC, Michael Ellerman wrote: > From: Alan Modra > > PowerPC64 uses the symbol .TOC. much as other targets use > _GLOBAL_OFFSET_TABLE_. It identifies the value of the GOT pointer (or in > powerpc parlance, the TOC pointer). Global offset tables are

Re: [PATCH 0/4] support for text-relative kallsyms table

On 21 January 2016 at 06:10, Rusty Russell wrote: > Ard Biesheuvel writes: >> This implements text-relative kallsyms address tables. This was developed >> as part of my series to implement KASLR/CONFIG_RELOCATABLE for arm64, but >> I think it may

[PATCH v3 2/9] selftests/powerpc: Test preservation of FPU and VMX regs across preemption

Loop in assembly checking the registers with many threads. Signed-off-by: Cyril Bur --- tools/testing/selftests/powerpc/math/.gitignore| 2 + tools/testing/selftests/powerpc/math/Makefile | 5 +- tools/testing/selftests/powerpc/math/fpu_asm.S | 34 +++

[PATCH] qe_ic: fix a buffer overflow error and add check elsewhere

127 is the theoretical up boundary of QEIC number, in fact there only be 44 qe_ic_info now. add check to overflow for qe_ic_info Signed-off-by: Zhao Qiang --- drivers/soc/fsl/qe/qe_ic.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git

Re: powerpc: Wire up copy_file_range() syscall

On Wed, 2016-13-01 at 16:50:22 UTC, Chandan Rajendra wrote: > Test runs on a ppc64 BE guest succeeded. > > Signed-off-by: Chandan Rajendra Applied to powerpc fixes, thanks. https://git.kernel.org/powerpc/c/d7f9ee60a6ebc263861a1d8c06 cheers

Re: [PATCH] powerpc/eeh: Fix PE location code

Sam Mendoza-Jonas writes: > On Wed, Jan 20, 2016 at 02:56:13PM +1100, Russell Currey wrote: >> On Wed, 2015-12-02 at 16:25 +1100, Gavin Shan wrote: >> > In eeh_pe_loc_get(), the PE location code is retrieved from the >> > "ibm,loc-code" property of the device node for the

Re: [PATCH 2/4] powerpc: enable text relative kallsyms for ppc64

On Wed, 2016-01-20 at 10:05 +0100, Ard Biesheuvel wrote: > This enables the newly introduced text-relative kallsyms support when > building 64-bit targets. This cuts the size of the kallsyms address > table in half, and drastically reduces the size of the PIE dynamic > relocation section when

Re: [PATCH] powerpc: remove newly added extra definition of pmd_dirty

On Thu, 2016-01-21 at 13:05 +1100, Stephen Rothwell wrote: > Commit d5d6a443b243 ("arch/powerpc/include/asm/pgtable-ppc64.h: > add pmd_[dirty|mkclean] for THP") added a new identical definition > of pdm_dirty. Remove it again. > > Cc: Minchan Kim > Cc: Andrew Morton

[PATCH] powerpc: remove newly added extra definition of pmd_dirty

Commit d5d6a443b243 ("arch/powerpc/include/asm/pgtable-ppc64.h: add pmd_[dirty|mkclean] for THP") added a new identical definition of pdm_dirty. Remove it again. Cc: Minchan Kim Cc: Andrew Morton Signed-off-by: Stephen Rothwell

Re: [PATCH] powerpc: remove newly added extra definition of pmd_dirty

On Thu, Jan 21, 2016 at 01:05:20PM +1100, Stephen Rothwell wrote: > Commit d5d6a443b243 ("arch/powerpc/include/asm/pgtable-ppc64.h: > add pmd_[dirty|mkclean] for THP") added a new identical definition > of pdm_dirty. Remove it again. > > Cc: Minchan Kim > Cc: Andrew Morton

Re: [PATCH 0/4] support for text-relative kallsyms table

Ard Biesheuvel writes: > This implements text-relative kallsyms address tables. This was developed > as part of my series to implement KASLR/CONFIG_RELOCATABLE for arm64, but > I think it may be beneficial to other architectures as well, so I am > presenting it as a

Re: powerpc: remove newly added extra definition of pmd_dirty

On Thu, 2016-21-01 at 02:05:20 UTC, Stephen Rothwell wrote: > Commit d5d6a443b243 ("arch/powerpc/include/asm/pgtable-ppc64.h: > add pmd_[dirty|mkclean] for THP") added a new identical definition > of pdm_dirty. Remove it again. > > Cc: Minchan Kim > Cc: Andrew Morton

[PATCH kernel v2 6/6] KVM: PPC: Add support for multiple-TCE hcalls

This adds real and virtual mode handlers for the H_PUT_TCE_INDIRECT and H_STUFF_TCE hypercalls for user space emulated devices such as IBMVIO devices or emulated PCI. These calls allow adding multiple entries (up to 512) into the TCE table in one call which saves time on transition between kernel

[PATCH kernel v2 0/6] KVM: PPC: Add in-kernel multitce handling

These patches enable in-kernel acceleration for H_PUT_TCE_INDIRECT and H_STUFF_TCE hypercalls which allow doing multiple (up to 512) TCE entries update in a single call saving time on switching context. QEMU already supports these hypercalls so this is just an optimization. Both HV and PR KVM

[PATCH kernel v2 4/6] KVM: PPC: Replace SPAPR_TCE_SHIFT with IOMMU_PAGE_SHIFT_4K

SPAPR_TCE_SHIFT is used in few places only and since IOMMU_PAGE_SHIFT_4K can be easily used instead, remove SPAPR_TCE_SHIFT. Signed-off-by: Alexey Kardashevskiy Reviewed-by: David Gibson --- arch/powerpc/include/asm/kvm_book3s_64.h | 2 --

[PATCH kernel v2 3/6] KVM: PPC: Account TCE-containing pages in locked_vm

At the moment pages used for TCE tables (in addition to pages addressed by TCEs) are not counted in locked_vm counter so a malicious userspace tool can call ioctl(KVM_CREATE_SPAPR_TCE) as many times as RLIMIT_NOFILE and lock a lot of memory. This adds counting for pages used for TCE tables. This

[PATCH kernel v2 1/6] KVM: PPC: Rework H_PUT_TCE/H_GET_TCE handlers

This reworks the existing H_PUT_TCE/H_GET_TCE handlers to have following patches applied nicer. This moves the ioba boundaries check to a helper and adds a check for least bits which have to be zeros. The patch is pretty mechanical (only check for least ioba bits is added) so no change in

[PATCH kernel v2 2/6] KVM: PPC: Use RCU for arch.spapr_tce_tables

At the moment spapr_tce_tables is not protected against races. This makes use of RCU-variants of list helpers. As some bits are executed in real mode, this makes use of just introduced list_for_each_entry_rcu_notrace(). This converts release_spapr_tce_table() to a RCU scheduled handler.

Re: [PATCH kernel v2 6/6] KVM: PPC: Add support for multiple-TCE hcalls

Hi Alexey, [auto build test ERROR on kvm/linux-next] [also build test ERROR on v4.4 next-20160121] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url:

[PATCH kernel] powerpc: Make vmalloc_to_phys() public

This makes vmalloc_to_phys() public as there will be another user (in-kernel VFIO acceleration) for it soon. As a part of future little optimization, this changes the helper to call vmalloc_to_pfn() instead of vmalloc_to_page() as the size of the struct page may not be power-of-two aligned which

[PATCH kernel v2 5/6] KVM: PPC: Move reusable bits of H_PUT_TCE handler to helpers

Upcoming multi-tce support (H_PUT_TCE_INDIRECT/H_STUFF_TCE hypercalls) will validate TCE (not to have unexpected bits) and IO address (to be within the DMA window boundaries). This introduces helpers to validate TCE and IO address. The helpers are exported as they compile into vmlinux (to work in

[PATCH v3 4/9] powerpc: Explicitly disable math features when copying thread

Currently when threads get scheduled off they always giveup the FPU, Altivec (VMX) and Vector (VSX) units if they were using them. When they are scheduled back on a fault is then taken to enable each facility and load registers. As a result explicitly disabling FPU/VMX/VSX has not been necessary.

[PATCH v3 1/9] selftests/powerpc: Test the preservation of FPU and VMX regs across syscall

Test that the non volatile floating point and Altivec registers get correctly preserved across the fork() syscall. fork() works nicely for this purpose, the registers should be the same for both parent and child Signed-off-by: Cyril Bur ---

[PATCH v3 5/9] powerpc: Restore FPU/VEC/VSX if previously used

Currently the FPU, VEC and VSX facilities are lazily loaded. This is not a problem unless a process is using these facilities. Modern versions of GCC are very good at automatically vectorising code, new and modernised workloads make use of floating point and vector facilities, even the kernel

[PATCH v3 9/9] powerpc: Add the ability to save VSX without giving it up

This patch adds the ability to be able to save the VSX registers to the thread struct without giving up (disabling the facility) next time the process returns to userspace. This patch builds on a previous optimisation for the FPU and VEC registers in the thread copy path to avoid a possibly

[PATCH v3 8/9] powerpc: Add the ability to save Altivec without giving it up

This patch adds the ability to be able to save the VEC registers to the thread struct without giving up (disabling the facility) next time the process returns to userspace. This patch builds on a previous optimisation for the FPU registers in the thread copy path to avoid a possibly pointless

[PATCH v3 7/9] powerpc: Add the ability to save FPU without giving it up

This patch adds the ability to be able to save the FPU registers to the thread struct without giving up (disabling the facility) next time the process returns to userspace. This patch optimises the thread copy path (as a result of a fork() or clone()) so that the parent thread can return to

[PATCH v3 6/9] powerpc: Prepare for splitting giveup_{fpu, altivec, vsx} in two

This prepares for the decoupling of saving {fpu,altivec,vsx} registers and marking {fpu,altivec,vsx} as being unused by a thread. Currently giveup_{fpu,altivec,vsx}() does both however optimisations to task switching can be made if these two operations are decoupled. save_all() will permit the

[PATCH v3 3/9] selftests/powerpc: Test FPU and VMX regs in signal ucontext

Load up the non volatile FPU and VMX regs and ensure that they are the expected value in a signal handler Signed-off-by: Cyril Bur --- tools/testing/selftests/powerpc/math/.gitignore | 2 + tools/testing/selftests/powerpc/math/Makefile | 4 +-

[PATCH v3 0/9] FP/VEC/VSX switching optimisations

Cover-letter for V1 of the series is at https://lists.ozlabs.org/pipermail/linuxppc-dev/2015-November/136350.html Cover-letter for V2 of the series is at https://lists.ozlabs.org/pipermail/linuxppc-dev/2016-January/138054.html Changes in V3: Addressed review comments from Michael Neuling - Made

Re: Different SIGSEGV codes (x86 and ppc64le)

On Tue, Jan 19, 2016 at 9:34 PM, Michael Ellerman wrote: > > The kernel describes those error codes as: > > #define SEGV_MAPERR (__SI_FAULT|1) /* address not mapped to object */ > #define SEGV_ACCERR (__SI_FAULT|2) /* invalid permissions for mapped > object */ > >

Re: [PATCH 1/4] kallsyms: add support for relative offsets in kallsyms address table

On Wed, Jan 20, 2016 at 1:05 AM, Ard Biesheuvel wrote: > Similar to how relative extables are implemented, it is possible to emit > the kallsyms table in such a way that it contains offsets relative to some > anchor point in the kernel image rather than absolute

Re: [PATCH 4/4] x86_64: enable text relative kallsyms for 64-bit targets

On Wed, Jan 20, 2016 at 1:05 AM, Ard Biesheuvel wrote: > This enables the newly introduced text-relative kallsyms support when > building 64-bit targets. This cuts the size of the kallsyms address > table in half, reducing the memory footprint of the kernel .rodata >

Re: [PATCH] powerpc/eeh: Fix PE location code

On Wed, Jan 20, 2016 at 02:56:13PM +1100, Russell Currey wrote: > On Wed, 2015-12-02 at 16:25 +1100, Gavin Shan wrote: > > In eeh_pe_loc_get(), the PE location code is retrieved from the > > "ibm,loc-code" property of the device node for the bridge of the > > PE's primary bus. It's not correct

[PATCH] powerpc: Enable VMX copy on PPC970 (G5)

There's no reason I'm aware of that the VMX copy loop shouldn't work on PPC970. And in fact it seems to boot and generally be happy. Signed-off-by: Michael Ellerman --- arch/powerpc/include/asm/cputable.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH 2/4] powerpc: enable text relative kallsyms for ppc64

This enables the newly introduced text-relative kallsyms support when building 64-bit targets. This cuts the size of the kallsyms address table in half, and drastically reduces the size of the PIE dynamic relocation section when building with CONFIG_RELOCATABLE=y (by about 3 MB for

[PATCH 0/4] support for text-relative kallsyms table

This implements text-relative kallsyms address tables. This was developed as part of my series to implement KASLR/CONFIG_RELOCATABLE for arm64, but I think it may be beneficial to other architectures as well, so I am presenting it as a separate series. The idea is that on 64-bit builds, it is

[PATCH 3/4] s390: enable text relative kallsyms for 64-bit targets

This enables the newly introduced text-relative kallsyms support when building 64-bit targets. This cuts the size of the kallsyms address table in half, reducing the memory footprint of the kernel .rodata section by about 250 KB for a defconfig build. Signed-off-by: Ard Biesheuvel

[PATCH 4/4] x86_64: enable text relative kallsyms for 64-bit targets

This enables the newly introduced text-relative kallsyms support when building 64-bit targets. This cuts the size of the kallsyms address table in half, reducing the memory footprint of the kernel .rodata section by about 400 KB for a KALLSYMS_ALL build, and about 100 KB reduction in compressed

[PATCH 1/4] kallsyms: add support for relative offsets in kallsyms address table

Similar to how relative extables are implemented, it is possible to emit the kallsyms table in such a way that it contains offsets relative to some anchor point in the kernel image rather than absolute addresses. The benefit is that such table entries are no longer subject to dynamic relocation

Re: [PATCH v5 0/9] ftrace with regs + live patching for ppc64 LE (ABI v2)

On Wed, Jan 20, 2016 at 05:03:23PM +1100, Michael Ellerman wrote: > On Wed, 2016-01-06 at 15:17 +0100, Petr Mladek wrote: > > On Fri 2015-12-04 15:45:29, Torsten Duwe wrote: > > > Changes since v4: > > > * change comment style in entry_64.S to C89 > > > (nobody is using assembler syntax

Re: [RFC PATCH v3 3/5] PCI: Add host bridge attribute to indicate filtering of MSIs is supported

On 2016/1/16 1:24, David Laight wrote: From: Yongji Xie Sent: 15 January 2016 07:06 MSI-X tables are not allowed to be mmapped in vfio-pci driver in case that user get to touch this directly. This will cause some performance issues when when PCI adapters have critical registers in the same

Re: [PATCH 3/4] s390: enable text relative kallsyms for 64-bit targets

On Wed, Jan 20, 2016 at 10:05:37AM +0100, Ard Biesheuvel wrote: > This enables the newly introduced text-relative kallsyms support when > building 64-bit targets. This cuts the size of the kallsyms address > table in half, reducing the memory footprint of the kernel .rodata > section by about 250

Re: [PATCH 3/4] s390: enable text relative kallsyms for 64-bit targets

On 20 January 2016 at 10:43, Heiko Carstens wrote: > On Wed, Jan 20, 2016 at 10:05:37AM +0100, Ard Biesheuvel wrote: >> This enables the newly introduced text-relative kallsyms support when >> building 64-bit targets. This cuts the size of the kallsyms address >> table

Re: [PATCH 3/4] s390: enable text relative kallsyms for 64-bit targets

On 20 January 2016 at 11:17, Heiko Carstens wrote: > On Wed, Jan 20, 2016 at 11:04:24AM +0100, Ard Biesheuvel wrote: >> On 20 January 2016 at 10:43, Heiko Carstens >> wrote: >> > On Wed, Jan 20, 2016 at 10:05:37AM +0100, Ard Biesheuvel

Re: [PATCH V10 2/4] perf/powerpc: add support for sampling intr machine state

On Mon, 2016-01-11 at 15:58 +0530, Anju T wrote: > diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig > index 9a7057e..c4ce60d 100644 > --- a/arch/powerpc/Kconfig > +++ b/arch/powerpc/Kconfig > @@ -119,6 +119,7 @@ config PPC > select GENERIC_ATOMIC64 if PPC32 > select

Re: [PATCH v5 0/9] ftrace with regs + live patching for ppc64 LE (ABI v2)

On Wed 2016-01-20 17:03:23, Michael Ellerman wrote: > On Wed, 2016-01-06 at 15:17 +0100, Petr Mladek wrote: > > On Fri 2015-12-04 15:45:29, Torsten Duwe wrote: > > > Changes since v4: > > > * change comment style in entry_64.S to C89 > > > (nobody is using assembler syntax comments there). >

Re: [PATCH 3/4] s390: enable text relative kallsyms for 64-bit targets

On Wed, Jan 20, 2016 at 11:04:24AM +0100, Ard Biesheuvel wrote: > On 20 January 2016 at 10:43, Heiko Carstens wrote: > > On Wed, Jan 20, 2016 at 10:05:37AM +0100, Ard Biesheuvel wrote: > >> This enables the newly introduced text-relative kallsyms support when > >>

Re: [PATCH v10 3/4] tools/perf: Map the ID values with register names

On Mon, 2016-01-11 at 15:58 +0530, Anju T wrote: > diff --git a/tools/perf/arch/powerpc/include/perf_regs.h > b/tools/perf/arch/powerpc/include/perf_regs.h > new file mode 100644 > index 000..93080f5 > --- /dev/null > +++ b/tools/perf/arch/powerpc/include/perf_regs.h > @@ -0,0 +1,64 @@ >

Re: [PATCH 0/4] support for text-relative kallsyms table

* Ard Biesheuvel wrote: > This implements text-relative kallsyms address tables. This was developed as > part of my series to implement KASLR/CONFIG_RELOCATABLE for arm64, but I > think > it may be beneficial to other architectures as well, so I am presenting it as

Re: [PATCH V10 1/4] perf/powerpc: assign an id to each powerpc register

Hi Anju, On Mon, 2016-01-11 at 15:58 +0530, Anju T wrote: > The enum definition assigns an 'id' to each register in "struct pt_regs" > of arch/powerpc. The order of these values in the enum definition are > based on the corresponding macros in arch/powerpc/include/uapi/asm/ptrace.h. Sorry one

Re: [PATCH 0/4] support for text-relative kallsyms table

On Wednesday 20 January 2016 11:33:25 Ingo Molnar wrote: > > The reduction ranges from around 250 KB uncompressed vmlinux size and 10 KB > > compressed size (s390) to 3 MB/500 KB for ppc64 (although, in the latter > > case, > > the reduction in uncompressed size is primarily __init data) > >

Re: [PATCH v9 2/6] Documentation, dt, arm64/arm: dt bindings for numa.

On Mon, Jan 18, 2016 at 10:06:01PM +0530, Ganapatrao Kulkarni wrote: > DT bindings for numa mapping of memory, cores and IOs. > > Reviewed-by: Robert Richter > Signed-off-by: Ganapatrao Kulkarni > --- >