[PATCH] tools/testing/selftests/powerpc: Add Anton's null_syscall benchmark to the selftests

[Rui Teng]

From: Anton Blanchard 

Pull in a version of Anton's null_syscall benchmark:
http://ozlabs.org/~anton/junkcode/null_syscall.c
Into tools/testing/selftests/powerpc/benchmarks.

Suggested-by: Michael Ellerman 
Signed-off-by: Anton Blanchard 
Signed-off-by: Rui Teng 
---
 .../testing/selftests/powerpc/benchmarks/Makefile  |   2 +-
 .../selftests/powerpc/benchmarks/null_syscall.c| 157 +
 2 files changed, 158 insertions(+), 1 deletion(-)
 create mode 100644 tools/testing/selftests/powerpc/benchmarks/null_syscall.c

diff --git a/tools/testing/selftests/powerpc/benchmarks/Makefile 
b/tools/testing/selftests/powerpc/benchmarks/Makefile
index a9adfb7..545077f 100644
--- a/tools/testing/selftests/powerpc/benchmarks/Makefile
+++ b/tools/testing/selftests/powerpc/benchmarks/Makefile
@@ -1,4 +1,4 @@
-TEST_PROGS := gettimeofday context_switch mmap_bench futex_bench
+TEST_PROGS := gettimeofday context_switch mmap_bench futex_bench null_syscall
 
 CFLAGS += -O2
 
diff --git a/tools/testing/selftests/powerpc/benchmarks/null_syscall.c 
b/tools/testing/selftests/powerpc/benchmarks/null_syscall.c
new file mode 100644
index 000..59c2f45
--- /dev/null
+++ b/tools/testing/selftests/powerpc/benchmarks/null_syscall.c
@@ -0,0 +1,157 @@
+/*
+ * Test null syscall performance
+ *
+ * Copyright (C) 2009-2015 Anton Blanchard , IBM
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#define NR_LOOPS 1000
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static volatile int soak_done;
+unsigned long long clock_frequency;
+unsigned long long timebase_frequency;
+double timebase_multiplier;
+
+static inline unsigned long long mftb(void)
+{
+   unsigned long low;
+
+   asm volatile("mftb %0" : "=r" (low));
+
+   return low;
+}
+
+static void sigalrm_handler(int unused)
+{
+   soak_done = 1;
+}
+
+/*
+ * Use a timer instead of busy looping on clock_gettime() so we don't
+ * pollute profiles with glibc and VDSO hits.
+ */
+static void cpu_soak_usecs(unsigned long usecs)
+{
+   struct itimerval val;
+
+   memset(, 0, sizeof(val));
+   val.it_value.tv_usec = usecs;
+
+   signal(SIGALRM, sigalrm_handler);
+   setitimer(ITIMER_REAL, , NULL);
+
+   while (1) {
+   if (soak_done)
+   break;
+   }
+
+   signal(SIGALRM, SIG_DFL);
+}
+
+/*
+ * This only works with recent kernels where cpufreq modifies
+ * /proc/cpuinfo dynamically.
+ */
+static void get_proc_frequency(void)
+{
+   FILE *f;
+   char line[128];
+   char *p, *end;
+   unsigned long v;
+   double d;
+   char *override;
+
+   /* Try to get out of low power/low frequency mode */
+   cpu_soak_usecs(0.25 * 100);
+
+   f = fopen("/proc/cpuinfo", "r");
+   if (f == NULL)
+   return;
+
+   timebase_frequency = 0;
+
+   while (fgets(line, sizeof(line), f) != NULL) {
+   if (strncmp(line, "timebase", 8) == 0) {
+   p = strchr(line, ':');
+   if (p != NULL) {
+   v = strtoull(p + 1, , 0);
+   if (end != p + 1)
+   timebase_frequency = v;
+   }
+   }
+
+   if (((strncmp(line, "clock", 5) == 0) ||
+(strncmp(line, "cpu MHz", 7) == 0))) {
+   p = strchr(line, ':');
+   if (p != NULL) {
+   d = strtod(p + 1, );
+   if (end != p + 1) {
+   /* Find fastest clock frequency */
+   if ((d * 100ULL) > clock_frequency)
+   clock_frequency = d * 
100ULL;
+   }
+   }
+   }
+   }
+
+   fclose(f);
+
+   override = getenv("FREQUENCY");
+   if (override)
+   clock_frequency = strtoull(override, NULL, 10);
+
+   if (timebase_frequency)
+   timebase_multiplier = (double)clock_frequency
+   / timebase_frequency;
+   else
+   timebase_multiplier = 1;
+}
+
+static void do_null_syscall(unsigned long nr)
+{
+   unsigned long i;
+
+   for (i = 0; i < nr; i++)
+   getppid();
+}
+
+#define TIME(A, STR) \
+
+int main(void)
+{
+   unsigned long tb_start, tb_now;
+   struct timespec tv_start, tv_now;
+   unsigned long long elapsed_ns, elapsed_tb;
+
+   get_proc_frequency();
+
+   

Re: [PATCH v21 00/20] perf, tools: Add support for PMU events in JSON format

[Jiri Olsa]

On Mon, Sep 26, 2016 at 09:59:54AM -0700, Andi Kleen wrote:
> On Mon, Sep 26, 2016 at 12:03:43PM -0300, Arnaldo Carvalho de Melo wrote:
> > Em Mon, Sep 26, 2016 at 10:35:33AM +0200, Jiri Olsa escreveu:
> > > ping.. is that working for you? IMO we can include this
> > > as additional patch to the set..
> > 
> > No, it doesn't fails to build on the first cross env I tried, fixing it
> > now, resulting patch:
> 
> Yes it shouldn't be difficult to fix cross building. I don't think
> there are any fundamental problems.

right, how about attached patch

Arnaldo,
could you please try it on cross build.. I still dont have setup for that :-\

thanks,
jirka


---
diff --git a/tools/build/Build b/tools/build/Build
index 63a6c34c0c88..76d1a4960973 100644
--- a/tools/build/Build
+++ b/tools/build/Build
@@ -1 +1,3 @@
+hostprogs := fixdep
+
 fixdep-y := fixdep.o
diff --git a/tools/build/Makefile b/tools/build/Makefile
index 0d5a0e3a8fa9..653faee2a055 100644
--- a/tools/build/Makefile
+++ b/tools/build/Makefile
@@ -14,6 +14,12 @@ endef
 $(call allow-override,CC,$(CROSS_COMPILE)gcc)
 $(call allow-override,LD,$(CROSS_COMPILE)ld)
 
+HOSTCC ?= gcc
+HOSTLD ?= ld
+HOSTAR ?= ar
+
+export HOSTCC HOSTLD HOSTAR
+
 ifeq ($(V),1)
   Q =
 else
diff --git a/tools/build/Makefile.build b/tools/build/Makefile.build
index 27f3583193e6..031c5631cc21 100644
--- a/tools/build/Makefile.build
+++ b/tools/build/Makefile.build
@@ -58,6 +58,9 @@ quiet_cmd_mkdir = MKDIR$(dir $@)
 quiet_cmd_cc_o_c = CC   $@
   cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
 
+quiet_cmd_host_cc_o_c = HOSTCC   $@
+  cmd_host_cc_o_c = $(HOSTCC) $(c_flags) -c -o $@ $<
+
 quiet_cmd_cpp_i_c = CPP  $@
   cmd_cpp_i_c = $(CC) $(c_flags) -E -o $@ $<
 
@@ -70,16 +73,24 @@ quiet_cmd_gen = GEN  $@
 # If there's nothing to link, create empty $@ object.
 quiet_cmd_ld_multi = LD   $@
   cmd_ld_multi = $(if $(strip $(obj-y)),\
-  $(LD) -r -o $@  $(filter $(obj-y),$^),rm -f $@; $(AR) 
rcs $@)
+ $(LD) -r -o $@  $(filter $(obj-y),$^),rm -f $@; $(AR) rcs 
$@)
+
+quiet_cmd_host_ld_multi = HOSTLD   $@
+  cmd_host_ld_multi = $(if $(strip $(obj-y)),\
+  $(HOSTLD) -r -o $@  $(filter $(obj-y),$^),rm -f $@; 
$(HOSTAR) rcs $@)
+
+ifneq ($(filter $(obj),$(hostprogs)),)
+  host = host_
+endif
 
 # Build rules
 $(OUTPUT)%.o: %.c FORCE
$(call rule_mkdir)
-   $(call if_changed_dep,cc_o_c)
+   $(call if_changed_dep,$(host)cc_o_c)
 
 $(OUTPUT)%.o: %.S FORCE
$(call rule_mkdir)
-   $(call if_changed_dep,cc_o_c)
+   $(call if_changed_dep,$(host)cc_o_c)
 
 $(OUTPUT)%.i: %.c FORCE
$(call rule_mkdir)
@@ -119,7 +130,7 @@ $(sort $(subdir-obj-y)): $(subdir-y) ;
 
 $(in-target): $(obj-y) FORCE
$(call rule_mkdir)
-   $(call if_changed,ld_multi)
+   $(call if_changed,$(host)ld_multi)
 
 __build: $(in-target)
@:
diff --git a/tools/build/Makefile.include b/tools/build/Makefile.include
index be630bed66d2..ad22e4e7bc59 100644
--- a/tools/build/Makefile.include
+++ b/tools/build/Makefile.include
@@ -1,10 +1,6 @@
 build := -f $(srctree)/tools/build/Makefile.build dir=. obj
 
-ifdef CROSS_COMPILE
-fixdep:
-else
 fixdep:
$(Q)$(MAKE) -C $(srctree)/tools/build CFLAGS= LDFLAGS= $(OUTPUT)fixdep
-endif
 
 .PHONY: fixdep
diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf
index 0abebcba849f..1347b5de3669 100644
--- a/tools/perf/Makefile.perf
+++ b/tools/perf/Makefile.perf
@@ -144,6 +144,10 @@ $(call allow-override,LD,$(CROSS_COMPILE)ld)
 
 LD += $(EXTRA_LDFLAGS)
 
+HOSTCC  ?= gcc
+HOSTLD  ?= ld
+HOSTAR  ?= ar
+
 PKG_CONFIG = $(CROSS_COMPILE)pkg-config
 
 RM  = rm -f
@@ -345,6 +349,7 @@ strip: $(PROGRAMS) $(OUTPUT)perf
 PERF_IN := $(OUTPUT)perf-in.o
 
 export srctree OUTPUT RM CC LD AR CFLAGS V BISON FLEX AWK
+export HOSTCC HOSTLD HOSTAR
 include $(srctree)/tools/build/Makefile.include
 
 JEVENTS   := $(OUTPUT)pmu-events/jevents
diff --git a/tools/perf/pmu-events/Build b/tools/perf/pmu-events/Build
index d2f34307ae79..9213a1273697 100644
--- a/tools/perf/pmu-events/Build
+++ b/tools/perf/pmu-events/Build
@@ -1,3 +1,5 @@
+hostprogs := jevents
+
 jevents-y  += json.o jsmn.o jevents.o
 pmu-events-y   += pmu-events.o
 JDIR   =  pmu-events/arch/$(ARCH)

Re: [PATCH] PCI: Add parameter @mmio_force_on to pci_update_resource()

[Benjamin Herrenschmidt]

On Tue, 2016-09-27 at 14:20 -0500, Bjorn Helgaas wrote:
> On Mon, Sep 19, 2016 at 09:53:30AM +1000, Gavin Shan wrote:
> > In pci_update_resource(), the PCI device's memory decoding (0x2 in
> > PCI_COMMAND) is disabled when 64-bits memory BAR is updated if the
> > PCI device's memory space wasn't asked to be always on by @pdev->
> > mmio_always_on. The PF's memory decoding might be disabled when
> > updating its IOV BARs in the following path. Actually, the PF's
> > memory decoding shouldn't be disabled in this scenario as the PF
> > has been started to provide services:
> 
> The reason we disable memory decoding while updating a 64-bit BAR is
> because we can't do the update atomically, and a half-updated BAR might
> conflict with other devices.
> 
> You need to explain what is special about these SR-IOV BARs that makes it
> safe to update them non-atomically while decoding is enabled.

The IOV BAR won't decode until SR-IOV is enabled right ? Gavin, I don't
think we update it "live", so it should be safe...

Cheers,
Ben.

Re: [PATCH v21 03/19] perf, tools: Use pmu_events table to create aliases

[Arnaldo Carvalho de Melo]

Em Thu, Sep 15, 2016 at 03:24:40PM -0700, Sukadev Bhattiprolu escreveu:
> At run time (when 'perf' is starting up), locate the specific table
> of PMU events that corresponds to the current CPU. Using that table,
> create aliases for the each of the PMU events in the CPU. The use
> these aliases to parse the user specified perf event.
> 
> In short this would allow the user to specify events using their
> aliases rather than raw event codes.
> 
> Based on input and some earlier patches from Andi Kleen, Jiri Olsa.

this took a long time so I'll try to go chainsawing some stuff along the
way, like why introduce a function that returns an error just to ignore
it, even more using a ugly (void) cast?

- Arnaldo
 
> Signed-off-by: Sukadev Bhattiprolu 
> Acked-by: Jiri Olsa 
> Acked-by: Ingo Molnar 
> ---
> 
> Changelog[v4]
>   - Split off unrelated code into separate patches.
> Changelog[v3]
>   - [Jiri Olsa] Fix memory leak in cpuid
> Changelog[v2]
>   - [Andi Kleen] Replace pmu_events_map->vfm with a generic "cpuid".
> ---
>  tools/perf/util/header.h |  1 +
>  tools/perf/util/pmu.c| 61 
> 
>  2 files changed, 62 insertions(+)
> 
> diff --git a/tools/perf/util/header.h b/tools/perf/util/header.h
> index d306ca1..d30109b 100644
> --- a/tools/perf/util/header.h
> +++ b/tools/perf/util/header.h
> @@ -151,4 +151,5 @@ int write_padded(int fd, const void *bf, size_t count, 
> size_t count_aligned);
>   */
>  int get_cpuid(char *buffer, size_t sz);
>  
> +char *get_cpuid_str(void);
>  #endif /* __PERF_HEADER_H */
> diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
> index 2babcdf..c842886 100644
> --- a/tools/perf/util/pmu.c
> +++ b/tools/perf/util/pmu.c
> @@ -12,6 +12,8 @@
>  #include "pmu.h"
>  #include "parse-events.h"
>  #include "cpumap.h"
> +#include "header.h"
> +#include "pmu-events/pmu-events.h"
>  
>  struct perf_pmu_format {
>   char *name;
> @@ -473,6 +475,62 @@ static struct cpu_map *pmu_cpumask(const char *name)
>   return cpus;
>  }
>  
> +/*
> + * Return the CPU id as a raw string.
> + *
> + * Each architecture should provide a more precise id string that
> + * can be use to match the architecture's "mapfile".
> + */
> +char * __weak get_cpuid_str(void)
> +{
> + return NULL;
> +}
> +
> +/*
> + * From the pmu_events_map, find the table of PMU events that corresponds
> + * to the current running CPU. Then, add all PMU events from that table
> + * as aliases.
> + */
> +static int pmu_add_cpu_aliases(struct list_head *head)
> +{
> + int i;
> + struct pmu_events_map *map;
> + struct pmu_event *pe;
> + char *cpuid;
> +
> + cpuid = get_cpuid_str();
> + if (!cpuid)
> + return 0;
> +
> + i = 0;
> + while (1) {
> + map = _events_map[i++];
> + if (!map->table)
> + goto out;
> +
> + if (!strcmp(map->cpuid, cpuid))
> + break;
> + }
> +
> + /*
> +  * Found a matching PMU events table. Create aliases
> +  */
> + i = 0;
> + while (1) {
> + pe = >table[i++];
> + if (!pe->name)
> + break;
> +
> + /* need type casts to override 'const' */
> + __perf_pmu__new_alias(head, NULL, (char *)pe->name,
> + (char *)pe->desc, (char *)pe->event);
> + }
> +
> +out:
> + free(cpuid);
> + return 0;
> +}
> +
>  struct perf_event_attr * __weak
>  perf_pmu__get_default_config(struct perf_pmu *pmu __maybe_unused)
>  {
> @@ -497,6 +555,9 @@ static struct perf_pmu *pmu_lookup(const char *name)
>   if (pmu_aliases(name, ))
>   return NULL;
>  
> + if (!strcmp(name, "cpu"))
> + (void)pmu_add_cpu_aliases();
> +
>   if (pmu_type(name, ))
>   return NULL;
>  
> -- 
> 1.8.3.1

Re: [v3,4/5] powerpc/pm: support deep sleep feature on T104x

[C.H. Zhao]

From: Scott Wood 
Sent: Sunday, September 25, 2016 3:24 PM
To: C.H. Zhao
Cc: linuxppc-dev@lists.ozlabs.org; linux-ker...@vger.kernel.org; 
z.chen...@gmail.com; Jason Jin
Subject: Re: [v3,4/5] powerpc/pm: support deep sleep feature on T104x
    
On Tue, Aug 02, 2016 at 07:59:31PM +0800, Chenhui Zhao wrote:
> T104x has deep sleep feature, which can switch off most parts of
> the SoC when it is in deep sleep mode. This way, it becomes more
> energy-efficient.
> 
> The DDR controller will also be powered off in deep sleep. Therefore,
> the last stage (the latter part of fsl_dp_enter_low) will run without DDR
> access. This piece of code and related TLBs are prefetched in advance.
> 
> Due to the different initialization code between 32-bit and 64-bit, they
> have separate resume entry and precedure.
> 
> The feature supports 32-bit and 64-bit kernel mode.
> 
> Signed-off-by: Chenhui Zhao 
> ---
>  arch/powerpc/include/asm/fsl_pm.h |  24 ++
>  arch/powerpc/kernel/asm-offsets.c |  12 +
>  arch/powerpc/kernel/fsl_booke_entry_mapping.S |  10 +
>  arch/powerpc/kernel/head_64.S |   2 +-
>  arch/powerpc/platforms/85xx/Makefile  |   1 +
>  arch/powerpc/platforms/85xx/deepsleep.c   | 278 ++
>  arch/powerpc/platforms/85xx/qoriq_pm.c    |  25 ++
>  arch/powerpc/platforms/85xx/t104x_deepsleep.S | 531 
>++
>  arch/powerpc/sysdev/fsl_rcpm.c    |   8 +-
>  9 files changed, 889 insertions(+), 2 deletions(-)
>  create mode 100644 arch/powerpc/platforms/85xx/deepsleep.c
>  create mode 100644 arch/powerpc/platforms/85xx/t104x_deepsleep.S
> 
> diff --git a/arch/powerpc/include/asm/fsl_pm.h 
> b/arch/powerpc/include/asm/fsl_pm.h
> index e05049b..48c2631 100644
> --- a/arch/powerpc/include/asm/fsl_pm.h
> +++ b/arch/powerpc/include/asm/fsl_pm.h
> @@ -20,6 +20,7 @@
>  
>  #define PLAT_PM_SLEEP    20
>  #define PLAT_PM_LPM20    30
> +#define PLAT_PM_LPM35    40
>  
>  #define FSL_PM_SLEEP (1 << 0)
>  #define FSL_PM_DEEP_SLEEP    (1 << 1)
> @@ -48,4 +49,27 @@ extern const struct fsl_pm_ops *qoriq_pm_ops;
>  
>  int __init fsl_rcpm_init(void);
>  
> +#ifdef CONFIG_FSL_QORIQ_PM
> +int fsl_enter_deepsleep(void);
> +int fsl_deepsleep_init(void);
> +#else
> +static inline int fsl_enter_deepsleep(void) { return -1; }
> +static inline int fsl_deepsleep_init(void) { return -1; }
> +#endif

Please return proper error codes.

Where can fsl_deepsleep_init() be called without CONFIG_FSL_QORIQ_PM?

[Chenhui] I can get rid of the ifdef here. And add it in 
arch/powerpc/sysdev/fsl_rcpm.c.

> +
> +extern void fsl_dp_enter_low(void *priv);
> +extern void fsl_booke_deep_sleep_resume(void);
> +
> +struct fsl_iomap {
> + void *ccsr_scfg_base;
> + void *ccsr_rcpm_base;
> + void *ccsr_ddr_base;
> + void *ccsr_gpio1_base;
> + void *ccsr_cpc_base;
> + void *dcsr_epu_base;
> + void *dcsr_npc_base;
> + void *dcsr_rcpm_base;
> + void *cpld_base;
> + void *fpga_base;
> +};

__iomem

[Chenhui] Yes. Will add it.

>  #endif /* __PPC_FSL_PM_H */
> diff --git a/arch/powerpc/kernel/asm-offsets.c 
> b/arch/powerpc/kernel/asm-offsets.c
> index 9ea0955..cc488f9 100644
> --- a/arch/powerpc/kernel/asm-offsets.c
> +++ b/arch/powerpc/kernel/asm-offsets.c
> @@ -68,6 +68,10 @@
>  #include "../mm/mmu_decl.h"
>  #endif
>  
> +#ifdef CONFIG_FSL_QORIQ_PM
> +#include 
> +#endif

I know this file ifdefs headers a lot, but it's generally not good
practice.  Does including this file cause any harm on other platforms?

[Chenhui] Not at all. Will remove it.

> diff --git a/arch/powerpc/kernel/fsl_booke_entry_mapping.S 
> b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
> index 83dd0f6..659b059 100644
> --- a/arch/powerpc/kernel/fsl_booke_entry_mapping.S
> +++ b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
> @@ -173,6 +173,10 @@ skpinv:  addi    r6,r6,1 /* 
> Increment */
>    lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_NEEDED)@h
>    ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_NEEDED)@l
>    mtspr   SPRN_MAS2,r6
> +#ifdef ENTRY_DEEPSLEEP_SETUP
> + LOAD_REG_IMMEDIATE(r8, MEMORY_START)
> + ori r8,r8,(MAS3_SX|MAS3_SW|MAS3_SR)
> +#endif
>    mtspr   SPRN_MAS3,r8
>    tlbwe
>  

Have you tried this with a relocatable kernel?

[Chenhui] Not yet. Not sure whether it has been supported on QorIQ platform.

> +static void fsl_dp_set_resume_pointer(void)
> +{
> + u32 resume_addr;
> +
> + /* the bootloader will finally jump to this address to return kernel */
> +#ifdef CONFIG_PPC32
> + resume_addr = (u32)(__pa(fsl_booke_deep_sleep_resume));
> +#else
> + resume_addr = (u32)(__pa(*(u64 *)fsl_booke_deep_sleep_resume)
> + & 0x);
> +#endif

Why are you masking the physical address by 0x?  Besides the
(u32) cast accomplishing the same thing, wouldn't it be a 

Re: [bug] crypto/vmx/p8_ghash memory corruption in 4.8-rc7

[Marcelo Cerri]

Hi,

On Tue, Sep 27, 2016 at 05:01:03AM -0400, Jan Stancek wrote:
> So, if we extended p8_ghash_desc_ctx to accommodate fallback_desc's ctx
> and then provided statesize/import/export, would that be acceptable?
> 
> struct p8_ghash_desc_ctx {
> ...
> struct shash_desc fallback_desc;
> +   char fallback_ctx[sizeof(struct ghash_desc_ctx)];
> 

I think so. That's the solution mentioned by Herbert. The only drawback
is that we will need to fix "ghash-generic" as the fallback
implementation in order to know beforehand its descsize.

However I would keep the p8_ghash_desc_ctx the way it is and I would
sum sizeof(struct ghash_desc_ctx) to the algorithm descsize instead.

Let me put a quick patch together to test this.

> 
> Also, does that mean that padlock_sha has similar problem?
> It does not seem to reserve any space for fallback __ctx and it calls
> init()/update()/export() with padlock_sha_desc's fallback:
> 
> struct padlock_sha_desc {
> struct shash_desc fallback;
> };
> 
> static struct shash_alg sha1_alg = {
> .descsize   =   sizeof(struct padlock_sha_desc),
> 

Yeah. It still seems to me that padlock-sha has the same problem. Maybe
we are missing something...

--
Regards,
Marcelo


signature.asc
Description: PGP signature

[PATCH] Fix "ibm,processor-radix-AP-encodings"

[Balbir Singh]

The top 3 bits of the lower order byte should contain the
AP encoding, we assume the top 3 bits of the MSB.

Signed-off-by: Balbir Singh 
---

 - Detected while reviewing Chris Smart's patch to add radix-AP-encoding
   to skiboot
 - Also fixed typo (sift/shift)

 arch/powerpc/mm/pgtable-radix.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c
index af897d9..d525b0b 100644
--- a/arch/powerpc/mm/pgtable-radix.c
+++ b/arch/powerpc/mm/pgtable-radix.c
@@ -245,10 +245,10 @@ static int __init radix_dt_scan_page_sizes(unsigned long 
node,
 
struct mmu_psize_def *def;
 
-   /* top 3 bit is AP encoding */
-   shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
-   ap = be32_to_cpu(prop[0]) >> 29;
-   pr_info("Page size sift = %d AP=0x%x\n", shift, ap);
+   /* top 3 bits of the lower order byte is AP encoding */
+   shift = be32_to_cpu(prop[0]) & 0x1f;
+   ap = (be32_to_cpu(prop[0]) >> 5) & 0x7;
+   pr_info("Page size shift = %d AP=0x%x\n", shift, ap);
 
idx = get_idx_from_shift(shift);
if (idx < 0)
-- 
2.5.5

Re: [PATCH] PCI: Add parameter @mmio_force_on to pci_update_resource()

[Gavin Shan]

On Wed, Sep 28, 2016 at 07:45:32AM +1000, Benjamin Herrenschmidt wrote:
>On Tue, 2016-09-27 at 14:20 -0500, Bjorn Helgaas wrote:
>> On Mon, Sep 19, 2016 at 09:53:30AM +1000, Gavin Shan wrote:
>> > In pci_update_resource(), the PCI device's memory decoding (0x2 in
>> > PCI_COMMAND) is disabled when 64-bits memory BAR is updated if the
>> > PCI device's memory space wasn't asked to be always on by @pdev->
>> > mmio_always_on. The PF's memory decoding might be disabled when
>> > updating its IOV BARs in the following path. Actually, the PF's
>> > memory decoding shouldn't be disabled in this scenario as the PF
>> > has been started to provide services:
>> 
>> The reason we disable memory decoding while updating a 64-bit BAR is
>> because we can't do the update atomically, and a half-updated BAR might
>> conflict with other devices.
>> 
>> You need to explain what is special about these SR-IOV BARs that makes it
>> safe to update them non-atomically while decoding is enabled.
>
>The IOV BAR won't decode until SR-IOV is enabled right ? Gavin, I don't
>think we update it "live", so it should be safe...
>

Yeah, it's safe to update it with memory decoding on. As the function call
flow I listed in the changelog (as below), nobody should access the IOV BAR
when pci_update_resource() is called. However, the PF's memory BARs might
be accessed that time and it's not safe to disable PF's memory decoding.

   sriov_numvfs_store
   pdev->driver->sriov_configure
   mlx5_core_sriov_configure
   pci_enable_sriov
   sriov_enable
   pcibios_sriov_enable
   pnv_pci_sriov_enable
   pnv_pci_vf_resource_shift
   pci_update_resource

Thanks,
Gavin

Re: [PATCH v2 5/5] drivers/pci/hotplug: Support surprise hotplug in powernv driver

[Gavin Shan]

On Mon, Sep 26, 2016 at 10:56:07PM +1000, Gavin Shan wrote:
>This supports PCI surprise hotplug. The design is highlighted as
>below:
>
>   * The PCI slot's surprise hotplug capability is exposed through
> device node property "ibm,slot-surprise-pluggable", meaning
> PCI surprise hotplug will be disabled if skiboot doesn't support
> it yet.
>   * The interrupt because of presence or link state change is raised
> on surprise hotplug event. One event is allocated and queued to
> the PCI slot for workqueue to pick it up and process in serialized
> fashion. The code flow for surprise hotplug is same to that for
> managed hotplug except: the affected PEs are put into frozen state
> to avoid unexpected EEH error reporting in surprise hot remove path.
>
>Signed-off-by: Gavin Shan 
>---

.../...

>+static irqreturn_t pnv_php_interrupt(int irq, void *data)
>+{
>+  struct pnv_php_slot *php_slot = data;
>+  struct pci_dev *pchild, *pdev = php_slot->pdev;
>+  struct eeh_dev *edev;
>+  struct eeh_pe *pe;
>+  struct pnv_php_event *event;
>+  u16 sts, lsts;
>+  u8 presence;
>+  bool added;
>+  unsigned long flags;
>+  int ret;
>+
>+  pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, );
>+  sts &= (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
>+  pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, sts);
>+  if (sts & PCI_EXP_SLTSTA_DLLSC) {
>+  pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, );
>+  added = !!(lsts & PCI_EXP_LNKSTA_DLLLA);
>+  } else if (sts & PCI_EXP_SLTSTA_PDC) {
>+  ret = pnv_pci_get_presence_state(php_slot->id, );
>+  if (!ret)
>+  return IRQ_HANDLED;
>+  added = !!(presence == OPAL_PCI_SLOT_PRESENT);
>+  } else {
>+  return IRQ_NONE;
>+  }
>+
>+  /* Freeze the removed PE to avoid unexpected error reporting */
>+  if (!added) {
>+  pchild = list_first_entry_or_null(_slot->bus->devices,
>+struct pci_dev, bus_list);
>+  edev = pchild ? pci_dev_to_eeh_dev(pchild) : NULL;
>+  pe = edev ? edev->pe : NULL;
>+  if (pe) {
>+  eeh_serialize_lock();
>+  eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
>+  eeh_serialize_unlock(flags);
>+  eeh_pe_set_option(pe, EEH_OPT_FREEZE_PE);
>+  }
>+  }
>+

I still need export @confirm_error_lock. Otherwise, it will be failed to be
built when having CONFIG_HOTPLUG_PCI_POWERNV=m. I will respin and add one
patch for that in v3.

Thanks,
Gavin

[PATCH v7] QE: remove PPCisms for QE

[Zhao Qiang]

QE was supported on PowerPC, and dependent on PPC,
Now it is supported on other platforms. so remove PPCisms.

Signed-off-by: Zhao Qiang 
---
Changes for v2:
- na
Changes for v3:
- add NO_IRQ
Changes for v4:
- modify spin_event_timeout to opencoded timeout loop
- remove NO_IRQ
- modify virq_to_hw to opencoed code
Changes for v5:
- modify commit msg
- modify depends of QUICC_ENGINE
- add kerneldoc header for qe_issue_cmd
Changes for v6:
- add dependency on FSL_SOC and PPC32 for drivers
  depending on QUICC_ENGING but not available on ARM
Changes for v7:
- split qeic part to another patch
- rebase

 drivers/net/ethernet/freescale/Kconfig | 10 ++---
 drivers/soc/fsl/qe/Kconfig |  2 +-
 drivers/soc/fsl/qe/qe.c| 80 --
 drivers/soc/fsl/qe/qe_io.c | 42 --
 drivers/soc/fsl/qe/qe_tdm.c|  8 ++--
 drivers/soc/fsl/qe/ucc.c   | 10 ++---
 drivers/soc/fsl/qe/ucc_fast.c  | 68 ++---
 drivers/tty/serial/Kconfig |  2 +-
 drivers/usb/gadget/udc/Kconfig |  2 +-
 drivers/usb/host/Kconfig   |  2 +-
 include/soc/fsl/qe/qe.h|  1 -
 11 files changed, 118 insertions(+), 109 deletions(-)

diff --git a/drivers/net/ethernet/freescale/Kconfig 
b/drivers/net/ethernet/freescale/Kconfig
index d1ca45f..6677aff 100644
--- a/drivers/net/ethernet/freescale/Kconfig
+++ b/drivers/net/ethernet/freescale/Kconfig
@@ -5,10 +5,10 @@
 config NET_VENDOR_FREESCALE
bool "Freescale devices"
default y
-   depends on FSL_SOC || QUICC_ENGINE || CPM1 || CPM2 || PPC_MPC512x || \
-  M523x || M527x || M5272 || M528x || M520x || M532x || \
-  ARCH_MXC || ARCH_MXS || (PPC_MPC52xx && PPC_BESTCOMM) || \
-  ARCH_LAYERSCAPE
+   depends on FSL_SOC || (QUICC_ENGINE && PPC32) || CPM1 || CPM2 || \
+  PPC_MPC512x || M523x || M527x || M5272 || M528x || M520x || \
+  M532x || ARCH_MXC || ARCH_MXS || \
+  (PPC_MPC52xx && PPC_BESTCOMM) || ARCH_LAYERSCAPE
---help---
  If you have a network (Ethernet) card belonging to this class, say Y.
 
@@ -72,7 +72,7 @@ config FSL_XGMAC_MDIO
 
 config UCC_GETH
tristate "Freescale QE Gigabit Ethernet"
-   depends on QUICC_ENGINE
+   depends on QUICC_ENGINE && FSL_SOC && PPC32
select FSL_PQ_MDIO
select PHYLIB
---help---
diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig
index 73a2e08..b26b643 100644
--- a/drivers/soc/fsl/qe/Kconfig
+++ b/drivers/soc/fsl/qe/Kconfig
@@ -4,7 +4,7 @@
 
 config QUICC_ENGINE
bool "Freescale QUICC Engine (QE) Support"
-   depends on FSL_SOC && PPC32
+   depends on OF && HAS_IOMEM
select GENERIC_ALLOCATOR
select CRC32
help
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 2707a82..2b53e85 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -33,8 +33,6 @@
 #include 
 #include 
 #include 
-#include 
-#include 
 
 static void qe_snums_init(void);
 static int qe_sdma_init(void);
@@ -109,15 +107,27 @@ void qe_reset(void)
panic("sdma init failed!");
 }
 
+/* issue commands to QE, return 0 on success while -EIO on error
+ *
+ * @cmd: the command code, should be QE_INIT_TX_RX, QE_STOP_TX and so on
+ * @device: which sub-block will run the command, QE_CR_SUBBLOCK_UCCFAST1 - 8
+ * , QE_CR_SUBBLOCK_UCCSLOW1 - 8, QE_CR_SUBBLOCK_MCC1 - 3,
+ * QE_CR_SUBBLOCK_IDMA1 - 4 and such on.
+ * @mcn_protocol: specifies mode for the command for non-MCC, should be
+ * QE_CR_PROTOCOL_HDLC_TRANSPARENT, QE_CR_PROTOCOL_QMC, QE_CR_PROTOCOL_UART
+ * and such on.
+ * @cmd_input: command related data.
+ */
 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
 {
unsigned long flags;
u8 mcn_shift = 0, dev_shift = 0;
-   u32 ret;
+   int ret;
+   int i;
 
spin_lock_irqsave(_lock, flags);
if (cmd == QE_RESET) {
-   out_be32(_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
+   iowrite32be((cmd | QE_CR_FLG), _immr->cp.cecr);
} else {
if (cmd == QE_ASSIGN_PAGE) {
/* Here device is the SNUM, not sub-block */
@@ -134,20 +144,26 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, 
u32 cmd_input)
mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
}
 
-   out_be32(_immr->cp.cecdr, cmd_input);
-   out_be32(_immr->cp.cecr,
-(cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
- mcn_protocol << mcn_shift));
+   iowrite32be(cmd_input, _immr->cp.cecdr);
+   iowrite32be((cmd | QE_CR_FLG | ((u32)device << dev_shift) |
+

[PATCH v6 1/4] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe

[Zhao Qiang]

move the driver from drivers/soc/fsl/qe to drivers/irqchip,
merge qe_ic.h and qe_ic.c into irq-qeic.c.

Signed-off-by: Zhao Qiang 
---
Changes for v2:
- modify the subject and commit msg
Changes for v3:
- merge .h file to .c, rename it with irq-qeic.c
Changes for v4:
- modify comments
Changes for v5:
- disable rename detection
Changes for v6:
- rebase

 drivers/irqchip/Makefile   |   1 +
 drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} |  95 ++-
 drivers/soc/fsl/qe/Makefile|   2 +-
 drivers/soc/fsl/qe/qe_ic.h | 103 -
 4 files changed, 94 insertions(+), 107 deletions(-)
 rename drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (85%)
 delete mode 100644 drivers/soc/fsl/qe/qe_ic.h

diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 4c203b6..face608 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI)  += irq-mvebu-odmi.o
 obj-$(CONFIG_LS_SCFG_MSI)  += irq-ls-scfg-msi.o
 obj-$(CONFIG_EZNPS_GIC)+= irq-eznps.o
 obj-$(CONFIG_ARCH_ASPEED)  += irq-aspeed-vic.o
+obj-$(CONFIG_QUICC_ENGINE) += irq-qeic.o
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/irqchip/irq-qeic.c
similarity index 85%
rename from drivers/soc/fsl/qe/qe_ic.c
rename to drivers/irqchip/irq-qeic.c
index ec2ca86..48ceded 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/irqchip/irq-qeic.c
@@ -1,7 +1,7 @@
 /*
- * arch/powerpc/sysdev/qe_lib/qe_ic.c
+ * drivers/irqchip/irq-qeic.c
  *
- * Copyright (C) 2006 Freescale Semiconductor, Inc.  All rights reserved.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.  All rights reserved.
  *
  * Author: Li Yang 
  * Based on code from Shlomi Gridish 
@@ -30,7 +30,96 @@
 #include 
 #include 
 
-#include "qe_ic.h"
+#define NR_QE_IC_INTS  64
+
+/* QE IC registers offset */
+#define QEIC_CICR  0x00
+#define QEIC_CIVEC 0x04
+#define QEIC_CRIPNR0x08
+#define QEIC_CIPNR 0x0c
+#define QEIC_CIPXCC0x10
+#define QEIC_CIPYCC0x14
+#define QEIC_CIPWCC0x18
+#define QEIC_CIPZCC0x1c
+#define QEIC_CIMR  0x20
+#define QEIC_CRIMR 0x24
+#define QEIC_CICNR 0x28
+#define QEIC_CIPRTA0x30
+#define QEIC_CIPRTB0x34
+#define QEIC_CRICR 0x3c
+#define QEIC_CHIVEC0x60
+
+/* Interrupt priority registers */
+#define CIPCC_SHIFT_PRI0   29
+#define CIPCC_SHIFT_PRI1   26
+#define CIPCC_SHIFT_PRI2   23
+#define CIPCC_SHIFT_PRI3   20
+#define CIPCC_SHIFT_PRI4   13
+#define CIPCC_SHIFT_PRI5   10
+#define CIPCC_SHIFT_PRI6   7
+#define CIPCC_SHIFT_PRI7   4
+
+/* CICR priority modes */
+#define CICR_GWCC  0x0004
+#define CICR_GXCC  0x0002
+#define CICR_GYCC  0x0001
+#define CICR_GZCC  0x0008
+#define CICR_GRTA  0x0020
+#define CICR_GRTB  0x0040
+#define CICR_HPIT_SHIFT8
+#define CICR_HPIT_MASK 0x0300
+#define CICR_HP_SHIFT  24
+#define CICR_HP_MASK   0x3f00
+
+/* CICNR */
+#define CICNR_WCC1T_SHIFT  20
+#define CICNR_ZCC1T_SHIFT  28
+#define CICNR_YCC1T_SHIFT  12
+#define CICNR_XCC1T_SHIFT  4
+
+/* CRICR */
+#define CRICR_RTA1T_SHIFT  20
+#define CRICR_RTB1T_SHIFT  28
+
+/* Signal indicator */
+#define SIGNAL_MASK3
+#define SIGNAL_HIGH2
+#define SIGNAL_LOW 0
+
+struct qe_ic {
+   /* Control registers offset */
+   volatile u32 __iomem *regs;
+
+   /* The remapper for this QEIC */
+   struct irq_domain *irqhost;
+
+   /* The "linux" controller struct */
+   struct irq_chip hc_irq;
+
+   /* VIRQ numbers of QE high/low irqs */
+   unsigned int virq_high;
+   unsigned int virq_low;
+};
+
+/*
+ * QE interrupt controller internal structure
+ */
+struct qe_ic_info {
+   /* location of this source at the QIMR register. */
+   u32 mask;
+
+   /* Mask register offset */
+   u32 mask_reg;
+
+   /*
+* for grouped interrupts sources - the interrupt
+* code as appears at the group priority register
+*/
+   u8  pri_code;
+
+   /* Group priority register offset */
+   u32 pri_reg;
+};
 
 static DEFINE_RAW_SPINLOCK(qe_ic_lock);
 
diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile
index 2031d38..51e4726 100644
--- a/drivers/soc/fsl/qe/Makefile
+++ b/drivers/soc/fsl/qe/Makefile
@@ -1,7 +1,7 @@
 #
 # Makefile for the linux ppc-specific parts of QE
 #
-obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o
+obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o 

[PATCH v3 0/6] powerpc/powernv: PCI Surprise Hotplug Support

[Gavin Shan]

This series of patches supports PCI surprise hotplug on PowerNV platform.
Without the corresponding skiboot patches, this feature won't be enabled
and workable.

   * The skiboot patches can be found in below link (PATCH[01/16):
 https://patchwork.ozlabs.org/project/skiboot/list/?submitter=63923
   * This newly added functionality depends on skiboot's changes. However,
 the functionality is disabled simply when skiboot doesn't support it.
 For one specific slot, property "ibm,slot-surprise-pluggable" of the
 slot's device node is set to 1 when surprise hotplug is claimed by
 skiboot.
   * The interrupts because of presence and link state change are enabled
 in order to support PCI surprise hotplug. The surprise hotplug events
 are queued to the PCI slot and they're picked up for further processing
 in serialized fashion. The surprise and managed hotplug share same code
 flow except: the affected PEs are put into frozen state to avoid unexpected
 EEH error reporting in surprise hot remove path.

PATCH[1/6] to PATCH[3/6] allow to freeze PEs to avoid unexpected EEH error
reporting in PCI surprise hot remove path. PATCH[4/6] clears PE's frozen state
on initializing it because the PE might have been put into frozen state in last
PCI surprise hot remove. PATCH[5/6] removes likely() and unlikely() in pnv_php.c
as they are not too useful. PATCH[6/6] supports PCI surprise hotplug for PowerNV
PCI hotplug driver.

Changelog
=
v2:
   * Add one patch to remove likely() and unlikely() in pnv_php.c.
   * Remove likely() and unlikely() in PATCH[v1 4/4].
   * The event isn't pre-allocated. It's always allocated from slab
 in the interrupt handler. The removed PE is put into frozen state
 before the event is allocated.
v3:
   * Add one patch to export confirm_error_lock to avoid building error
 when having CONFIG_HOTPLUG_PCI_POWERNV=m

Gavin Shan (6):
  powerpc/eeh: Allow to freeze PE in eeh_pe_set_option()
  powerpc/eeh: Export confirm_error_lock
  powerpc/eeh: Export eeh_pe_state_mark()
  powerpc/powernv: Unfreeze PE on allocation
  drivers/pci/hotplug: Remove likely() and unlikely() in powernv driver
  drivers/pci/hotplug: Support surprise hotplug in powernv driver

 arch/powerpc/include/asm/pnv-pci.h|   2 +
 arch/powerpc/kernel/eeh.c |   2 +
 arch/powerpc/kernel/eeh_pe.c  |   1 +
 arch/powerpc/platforms/powernv/pci-ioda.c |  12 ++
 drivers/pci/hotplug/pnv_php.c | 268 ++
 5 files changed, 257 insertions(+), 28 deletions(-)

-- 
2.1.0

[PATCH v3 2/6] powerpc/eeh: Export confirm_error_lock

[Gavin Shan]

This exports @confirm_error_lock so that eeh_serialize_{lock, unlock}()
can be used to freeze the affected PE in PCI surprise hot remove path.

Signed-off-by: Gavin Shan 
---
 arch/powerpc/kernel/eeh.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index 0699f15..130bcae 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -116,6 +116,7 @@ struct eeh_ops *eeh_ops = NULL;
 
 /* Lock to avoid races due to multiple reports of an error */
 DEFINE_RAW_SPINLOCK(confirm_error_lock);
+EXPORT_SYMBOL_GPL(confirm_error_lock);
 
 /* Lock to protect passed flags */
 static DEFINE_MUTEX(eeh_dev_mutex);
-- 
2.1.0

[PATCH v3 1/6] powerpc/eeh: Allow to freeze PE in eeh_pe_set_option()

[Gavin Shan]

Function eeh_pe_set_option() is used to apply the requested options
(enable, disable, unfreeze) in EEH virtualization path. The semantics
of this function isn't complete until freezing is supported.

This allows to freeze the indicated PE. The new semantics is going to
be used in PCI surprise hot remove path, to freeze removed PCI devices
(PE) to avoid unexpected EEH error reporting.

Signed-off-by: Gavin Shan 
---
 arch/powerpc/kernel/eeh.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index 7429556..0699f15 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -1502,6 +1502,7 @@ int eeh_pe_set_option(struct eeh_pe *pe, int option)
break;
case EEH_OPT_THAW_MMIO:
case EEH_OPT_THAW_DMA:
+   case EEH_OPT_FREEZE_PE:
if (!eeh_ops || !eeh_ops->set_option) {
ret = -ENOENT;
break;
-- 
2.1.0

[PATCH v3 6/6] drivers/pci/hotplug: Support surprise hotplug in powernv driver

[Gavin Shan]

This supports PCI surprise hotplug. The design is highlighted as
below:

   * The PCI slot's surprise hotplug capability is exposed through
 device node property "ibm,slot-surprise-pluggable", meaning
 PCI surprise hotplug will be disabled if skiboot doesn't support
 it yet.
   * The interrupt because of presence or link state change is raised
 on surprise hotplug event. One event is allocated and queued to
 the PCI slot for workqueue to pick it up and process in serialized
 fashion. The code flow for surprise hotplug is same to that for
 managed hotplug except: the affected PEs are put into frozen state
 to avoid unexpected EEH error reporting in surprise hot remove path.

Signed-off-by: Gavin Shan 
---
 arch/powerpc/include/asm/pnv-pci.h |   2 +
 drivers/pci/hotplug/pnv_php.c  | 212 +
 2 files changed, 214 insertions(+)

diff --git a/arch/powerpc/include/asm/pnv-pci.h 
b/arch/powerpc/include/asm/pnv-pci.h
index 0cbd813..17e89dd 100644
--- a/arch/powerpc/include/asm/pnv-pci.h
+++ b/arch/powerpc/include/asm/pnv-pci.h
@@ -60,6 +60,8 @@ struct pnv_php_slot {
 #define PNV_PHP_STATE_POPULATED2
 #define PNV_PHP_STATE_OFFLINE  3
int state;
+   int irq;
+   struct workqueue_struct *wq;
struct device_node  *dn;
struct pci_dev  *pdev;
struct pci_bus  *bus;
diff --git a/drivers/pci/hotplug/pnv_php.c b/drivers/pci/hotplug/pnv_php.c
index 182f218..ea4ec72d 100644
--- a/drivers/pci/hotplug/pnv_php.c
+++ b/drivers/pci/hotplug/pnv_php.c
@@ -22,6 +22,12 @@
 #define DRIVER_AUTHOR  "Gavin Shan, IBM Corporation"
 #define DRIVER_DESC"PowerPC PowerNV PCI Hotplug Driver"
 
+struct pnv_php_event {
+   booladded;
+   struct pnv_php_slot *php_slot;
+   struct work_struct  work;
+};
+
 static LIST_HEAD(pnv_php_slot_list);
 static DEFINE_SPINLOCK(pnv_php_lock);
 
@@ -29,12 +35,40 @@ static void pnv_php_register(struct device_node *dn);
 static void pnv_php_unregister_one(struct device_node *dn);
 static void pnv_php_unregister(struct device_node *dn);
 
+static void pnv_php_disable_irq(struct pnv_php_slot *php_slot)
+{
+   struct pci_dev *pdev = php_slot->pdev;
+   u16 ctrl;
+
+   if (php_slot->irq > 0) {
+   pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, );
+   ctrl &= ~(PCI_EXP_SLTCTL_HPIE |
+ PCI_EXP_SLTCTL_PDCE |
+ PCI_EXP_SLTCTL_DLLSCE);
+   pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, ctrl);
+
+   free_irq(php_slot->irq, php_slot);
+   php_slot->irq = 0;
+   }
+
+   if (php_slot->wq) {
+   destroy_workqueue(php_slot->wq);
+   php_slot->wq = NULL;
+   }
+
+   if (pdev->msix_enabled)
+   pci_disable_msix(pdev);
+   else if (pdev->msi_enabled)
+   pci_disable_msi(pdev);
+}
+
 static void pnv_php_free_slot(struct kref *kref)
 {
struct pnv_php_slot *php_slot = container_of(kref,
struct pnv_php_slot, kref);
 
WARN_ON(!list_empty(_slot->children));
+   pnv_php_disable_irq(php_slot);
kfree(php_slot->name);
kfree(php_slot);
 }
@@ -609,6 +643,179 @@ static int pnv_php_register_slot(struct pnv_php_slot 
*php_slot)
return 0;
 }
 
+static int pnv_php_enable_msix(struct pnv_php_slot *php_slot)
+{
+   struct pci_dev *pdev = php_slot->pdev;
+   struct msix_entry entry;
+   int nr_entries, ret;
+   u16 pcie_flag;
+
+   /* Get total number of MSIx entries */
+   nr_entries = pci_msix_vec_count(pdev);
+   if (nr_entries < 0)
+   return nr_entries;
+
+   /* Check hotplug MSIx entry is in range */
+   pcie_capability_read_word(pdev, PCI_EXP_FLAGS, _flag);
+   entry.entry = (pcie_flag & PCI_EXP_FLAGS_IRQ) >> 9;
+   if (entry.entry >= nr_entries)
+   return -ERANGE;
+
+   /* Enable MSIx */
+   ret = pci_enable_msix_exact(pdev, , 1);
+   if (ret) {
+   dev_warn(>dev, "Error %d enabling MSIx\n", ret);
+   return ret;
+   }
+
+   return entry.vector;
+}
+
+static void pnv_php_event_handler(struct work_struct *work)
+{
+   struct pnv_php_event *event =
+   container_of(work, struct pnv_php_event, work);
+   struct pnv_php_slot *php_slot = event->php_slot;
+
+   if (event->added)
+   pnv_php_enable_slot(_slot->slot);
+   else
+   pnv_php_disable_slot(_slot->slot);
+
+   kfree(event);
+}
+
+static irqreturn_t pnv_php_interrupt(int irq, void *data)
+{
+   struct pnv_php_slot *php_slot = data;
+   struct pci_dev *pchild, *pdev = php_slot->pdev;
+   struct eeh_dev *edev;
+   struct eeh_pe *pe;
+  

[PATCH v3 3/6] powerpc/eeh: Export eeh_pe_state_mark()

[Gavin Shan]

This exports eeh_pe_state_mark(). It will be used to mark the surprise
hot removed PE as isolated to avoid unexpected EEH error reporting in
surprise remove path.

Signed-off-by: Gavin Shan 
---
 arch/powerpc/kernel/eeh_pe.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/kernel/eeh_pe.c b/arch/powerpc/kernel/eeh_pe.c
index f0520da..de7d091 100644
--- a/arch/powerpc/kernel/eeh_pe.c
+++ b/arch/powerpc/kernel/eeh_pe.c
@@ -581,6 +581,7 @@ void eeh_pe_state_mark(struct eeh_pe *pe, int state)
 {
eeh_pe_traverse(pe, __eeh_pe_state_mark, );
 }
+EXPORT_SYMBOL_GPL(eeh_pe_state_mark);
 
 static void *__eeh_pe_dev_mode_mark(void *data, void *flag)
 {
-- 
2.1.0

Re: [PATCH v5] powerpc: Do not make the entire heap executable

[Jason Gunthorpe]

On Wed, Sep 28, 2016 at 11:42:11AM +1000, Michael Ellerman wrote:

> But this is not really a powerpc patch, and I'm not an ELF expert. So
> I'm not comfortable merging it via the powerpc tree. It doesn't look
> like we really have a maintainer for binfmt_elf.c, so I'm not sure who
> should be acking that part.

Thanks a bunch for looking at this Michael.

> I've added Al Viro to Cc, he maintains fs/ and might be interested.

> I've also added Andrew Morton who might be happy to put this in his
> tree, and see if anyone complains?

For those added to the CC, I would re-state my original commit message
more clearly.

My research showed that the ELF loader bug fixed in this patch is the
root cause bug fix required to implement this hunk:

> > -#define VM_DATA_DEFAULT_FLAGS32(VM_READ | VM_WRITE | VM_EXEC | \
> > +#define VM_DATA_DEFAULT_FLAGS32 \
> > +   (((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \
> > +VM_READ | VM_WRITE | \
> >  VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)

Eg that 32 bit powerpc currently unconditionally injects writable,
executable pages into a user space process.

This critically undermines all the W^X security work that has been
done in the tool chain and user space by the PPC community.

I would encourage people to view this as an important security patch
for 32 bit powerpc environments.

Regards,
Jason

[PATCH v6 3/4] irqchip/qeic: merge qeic_of_init into qe_ic_init

[Zhao Qiang]

qeic_of_init just get device_node of qeic from dtb and call qe_ic_init,
pass the device_node to qe_ic_init.
So merge qeic_of_init into qe_ic_init to get the qeic node in
qe_ic_init.

Signed-off-by: Zhao Qiang 
---
Changes for v2:
- modify subject and commit msg
- return 0 and add put node when return in qe_ic_init
Changes for v3:
- na
Changes for v4:
- na
Changes for v5:
- na
Changes for v6:
- rebase

 drivers/irqchip/irq-qeic.c | 91 +-
 include/soc/fsl/qe/qe_ic.h |  7 
 2 files changed, 50 insertions(+), 48 deletions(-)

diff --git a/drivers/irqchip/irq-qeic.c b/drivers/irqchip/irq-qeic.c
index 1463731..4f49d4b 100644
--- a/drivers/irqchip/irq-qeic.c
+++ b/drivers/irqchip/irq-qeic.c
@@ -406,27 +406,38 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
return irq_linear_revmap(qe_ic->irqhost, irq);
 }
 
-void __init qe_ic_init(struct device_node *node, unsigned int flags,
-  void (*low_handler)(struct irq_desc *desc),
-  void (*high_handler)(struct irq_desc *desc))
+static int __init qe_ic_init(unsigned int flags)
 {
+   struct device_node *node;
struct qe_ic *qe_ic;
struct resource res;
-   u32 temp = 0, ret, high_active = 0;
+   u32 temp = 0, high_active = 0;
+   int ret = 0;
+
+   node = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
+   if (!node) {
+   node = of_find_node_by_type(NULL, "qeic");
+   if (!node)
+   return -ENODEV;
+   }
 
ret = of_address_to_resource(node, 0, );
-   if (ret)
-   return;
+   if (ret) {
+   ret = -ENODEV;
+   goto err_put_node;
+   }
 
qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
-   if (qe_ic == NULL)
-   return;
+   if (qe_ic == NULL) {
+   ret = -ENOMEM;
+   goto err_put_node;
+   }
 
qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,
   _ic_host_ops, qe_ic);
if (qe_ic->irqhost == NULL) {
-   kfree(qe_ic);
-   return;
+   ret = -ENOMEM;
+   goto err_free_qe_ic;
}
 
qe_ic->regs = ioremap(res.start, resource_size());
@@ -437,9 +448,9 @@ void __init qe_ic_init(struct device_node *node, unsigned 
int flags,
qe_ic->virq_low = irq_of_parse_and_map(node, 1);
 
if (qe_ic->virq_low == NO_IRQ) {
-   printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
-   kfree(qe_ic);
-   return;
+   pr_err("Failed to map QE_IC low IRQ\n");
+   ret = -ENOMEM;
+   goto err_domain_remove;
}
 
/* default priority scheme is grouped. If spread mode is*/
@@ -466,13 +477,24 @@ void __init qe_ic_init(struct device_node *node, unsigned 
int flags,
qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
 
irq_set_handler_data(qe_ic->virq_low, qe_ic);
-   irq_set_chained_handler(qe_ic->virq_low, low_handler);
+   irq_set_chained_handler(qe_ic->virq_low, qe_ic_cascade_low_mpic);
 
if (qe_ic->virq_high != NO_IRQ &&
qe_ic->virq_high != qe_ic->virq_low) {
irq_set_handler_data(qe_ic->virq_high, qe_ic);
-   irq_set_chained_handler(qe_ic->virq_high, high_handler);
+   irq_set_chained_handler(qe_ic->virq_high,
+   qe_ic_cascade_high_mpic);
}
+   of_node_put(node);
+   return 0;
+
+err_domain_remove:
+   irq_domain_remove(qe_ic->irqhost);
+err_free_qe_ic:
+   kfree(qe_ic);
+err_put_node:
+   of_node_put(node);
+   return ret;
 }
 
 void qe_ic_set_highest_priority(unsigned int virq, int high)
@@ -579,39 +601,26 @@ static struct device device_qe_ic = {
.bus = _ic_subsys,
 };
 
-static int __init init_qe_ic_sysfs(void)
+static int __init init_qe_ic(void)
 {
-   int rc;
+   int ret;
 
-   printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
+   ret = qe_ic_init(0);
+   if (ret)
+   return ret;
 
-   rc = subsys_system_register(_ic_subsys, NULL);
-   if (rc) {
-   printk(KERN_ERR "Failed registering qe_ic sys class\n");
+   ret = subsys_system_register(_ic_subsys, NULL);
+   if (ret) {
+   pr_err("Failed registering qe_ic sys class\n");
return -ENODEV;
}
-   rc = device_register(_qe_ic);
-   if (rc) {
-   printk(KERN_ERR "Failed registering qe_ic sys device\n");
+   ret = device_register(_qe_ic);
+   if (ret) {
+   pr_err("Failed registering qe_ic sys device\n");
return -ENODEV;
}
-   return 0;
-}
-
-static int __init qeic_of_init(void)
-{
-   struct device_node *np;
 
-   np = 

[PATCH v6 4/4] irqchip/qeic: remove PPCisms for QEIC

[Zhao Qiang]

QEIC was supported on PowerPC, and dependent on PPC,
Now it is supported on other platforms, so remove PPCisms.

Signed-off-by: Zhao Qiang 
---
Changes for v6:
- new added

 drivers/irqchip/irq-qeic.c | 28 +---
 include/soc/fsl/qe/qe_ic.h | 12 ++--
 2 files changed, 23 insertions(+), 17 deletions(-)

diff --git a/drivers/irqchip/irq-qeic.c b/drivers/irqchip/irq-qeic.c
index 4f49d4b..98a8b38 100644
--- a/drivers/irqchip/irq-qeic.c
+++ b/drivers/irqchip/irq-qeic.c
@@ -18,7 +18,10 @@
 #include 
 #include 
 #include 
+#include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -266,13 +269,13 @@ static struct qe_ic_info qe_ic_info[] = {
 
 static inline u32 qe_ic_read(volatile __be32  __iomem * base, unsigned int reg)
 {
-   return in_be32(base + (reg >> 2));
+   return ioread32be(base + (reg >> 2));
 }
 
 static inline void qe_ic_write(volatile __be32  __iomem * base, unsigned int 
reg,
   u32 value)
 {
-   out_be32(base + (reg >> 2), value);
+   iowrite32be(value, base + (reg >> 2));
 }
 
 static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
@@ -374,7 +377,7 @@ static const struct irq_domain_ops qe_ic_host_ops = {
.xlate = irq_domain_xlate_onetwocell,
 };
 
-/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
+/* Return an interrupt vector or 0 if no interrupt is pending. */
 unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
 {
int irq;
@@ -385,12 +388,12 @@ unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
 
if (irq == 0)
-   return NO_IRQ;
+   return 0;
 
return irq_linear_revmap(qe_ic->irqhost, irq);
 }
 
-/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
+/* Return an interrupt vector or 0 if no interrupt is pending. */
 unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
 {
int irq;
@@ -401,7 +404,7 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
 
if (irq == 0)
-   return NO_IRQ;
+   return 0;
 
return irq_linear_revmap(qe_ic->irqhost, irq);
 }
@@ -447,7 +450,7 @@ static int __init qe_ic_init(unsigned int flags)
qe_ic->virq_high = irq_of_parse_and_map(node, 0);
qe_ic->virq_low = irq_of_parse_and_map(node, 1);
 
-   if (qe_ic->virq_low == NO_IRQ) {
+   if (qe_ic->virq_low == 0) {
pr_err("Failed to map QE_IC low IRQ\n");
ret = -ENOMEM;
goto err_domain_remove;
@@ -479,7 +482,7 @@ static int __init qe_ic_init(unsigned int flags)
irq_set_handler_data(qe_ic->virq_low, qe_ic);
irq_set_chained_handler(qe_ic->virq_low, qe_ic_cascade_low_mpic);
 
-   if (qe_ic->virq_high != NO_IRQ &&
+   if (qe_ic->virq_high != 0 &&
qe_ic->virq_high != qe_ic->virq_low) {
irq_set_handler_data(qe_ic->virq_high, qe_ic);
irq_set_chained_handler(qe_ic->virq_high,
@@ -500,7 +503,8 @@ err_put_node:
 void qe_ic_set_highest_priority(unsigned int virq, int high)
 {
struct qe_ic *qe_ic = qe_ic_from_irq(virq);
-   unsigned int src = virq_to_hw(virq);
+   struct irq_data *irq_data = irq_get_irq_data(virq);
+   irq_hw_number_t src = WARN_ON(!irq_data) ? 0 : irq_data->hwirq;
u32 temp = 0;
 
temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
@@ -518,7 +522,8 @@ void qe_ic_set_highest_priority(unsigned int virq, int high)
 int qe_ic_set_priority(unsigned int virq, unsigned int priority)
 {
struct qe_ic *qe_ic = qe_ic_from_irq(virq);
-   unsigned int src = virq_to_hw(virq);
+   struct irq_data *irq_data = irq_get_irq_data(virq);
+   irq_hw_number_t src = WARN_ON(!irq_data) ? 0 : irq_data->hwirq;
u32 temp;
 
if (priority > 8 || priority == 0)
@@ -548,7 +553,8 @@ int qe_ic_set_priority(unsigned int virq, unsigned int 
priority)
 int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
 {
struct qe_ic *qe_ic = qe_ic_from_irq(virq);
-   unsigned int src = virq_to_hw(virq);
+   struct irq_data *irq_data = irq_get_irq_data(virq);
+   irq_hw_number_t src = WARN_ON(!irq_data) ? 0 : irq_data->hwirq;
u32 temp, control_reg = QEIC_CICNR, shift = 0;
 
if (priority > 2 || priority == 0)
diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
index 6113699..863cfec 100644
--- a/include/soc/fsl/qe/qe_ic.h
+++ b/include/soc/fsl/qe/qe_ic.h
@@ -76,7 +76,7 @@ static inline void qe_ic_cascade_low_ipic(struct irq_desc 
*desc)
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
 
-   if (cascade_irq != NO_IRQ)
+   if (cascade_irq != 0)
generic_handle_irq(cascade_irq);
 }
 
@@ -85,7 +85,7 @@ 

[PATCH v6 2/4] irqchip/qeic: merge qeic init code from platforms to a common function

[Zhao Qiang]

The codes of qe_ic init from a variety of platforms are redundant,
merge them to a common function and put it to irqchip/irq-qeic.c

For non-p1021_mds mpc85xx_mds boards, use "qe_ic_init(np, 0,
qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);" instead of
"qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);".

qe_ic_cascade_muxed_mpic was used for boards has the same interrupt
number for low interrupt and high interrupt, qe_ic_init has checked
if "low interrupt == high interrupt"

Signed-off-by: Zhao Qiang 
---
Changes for v2:
- modify subject and commit msg
- add check for qeic by type
Changes for v3:
- na
Changes for v4:
- na
Changes for v5:
- na
Changes for v6:
- rebase

 arch/powerpc/platforms/83xx/misc.c| 15 ---
 arch/powerpc/platforms/85xx/corenet_generic.c |  9 -
 arch/powerpc/platforms/85xx/mpc85xx_mds.c | 14 --
 arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 16 
 arch/powerpc/platforms/85xx/twr_p102x.c   | 14 --
 drivers/irqchip/irq-qeic.c| 16 
 6 files changed, 16 insertions(+), 68 deletions(-)

diff --git a/arch/powerpc/platforms/83xx/misc.c 
b/arch/powerpc/platforms/83xx/misc.c
index d75c981..c09a135 100644
--- a/arch/powerpc/platforms/83xx/misc.c
+++ b/arch/powerpc/platforms/83xx/misc.c
@@ -93,24 +93,9 @@ void __init mpc83xx_ipic_init_IRQ(void)
 }
 
 #ifdef CONFIG_QUICC_ENGINE
-void __init mpc83xx_qe_init_IRQ(void)
-{
-   struct device_node *np;
-
-   np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
-   if (!np) {
-   np = of_find_node_by_type(NULL, "qeic");
-   if (!np)
-   return;
-   }
-   qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
-   of_node_put(np);
-}
-
 void __init mpc83xx_ipic_and_qe_init_IRQ(void)
 {
mpc83xx_ipic_init_IRQ();
-   mpc83xx_qe_init_IRQ();
 }
 #endif /* CONFIG_QUICC_ENGINE */
 
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c 
b/arch/powerpc/platforms/85xx/corenet_generic.c
index 1179115..1d96c3f 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -41,8 +41,6 @@ void __init corenet_gen_pic_init(void)
unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
MPIC_NO_RESET;
 
-   struct device_node *np;
-
if (ppc_md.get_irq == mpic_get_coreint_irq)
flags |= MPIC_ENABLE_COREINT;
 
@@ -50,13 +48,6 @@ void __init corenet_gen_pic_init(void)
BUG_ON(mpic == NULL);
 
mpic_init(mpic);
-
-   np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
-   if (np) {
-   qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
-   qe_ic_cascade_high_mpic);
-   of_node_put(np);
-   }
 }
 
 /*
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c 
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index d7e440e..06f34a9 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -283,20 +283,6 @@ static void __init mpc85xx_mds_qeic_init(void)
of_node_put(np);
return;
}
-
-   np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
-   if (!np) {
-   np = of_find_node_by_type(NULL, "qeic");
-   if (!np)
-   return;
-   }
-
-   if (machine_is(p1021_mds))
-   qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
-   qe_ic_cascade_high_mpic);
-   else
-   qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
-   of_node_put(np);
 }
 #else
 static void __init mpc85xx_mds_qe_init(void) { }
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c 
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 1006950..000d385 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -48,10 +48,6 @@ void __init mpc85xx_rdb_pic_init(void)
 {
struct mpic *mpic;
 
-#ifdef CONFIG_QUICC_ENGINE
-   struct device_node *np;
-#endif
-
if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) {
mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
MPIC_BIG_ENDIAN |
@@ -66,18 +62,6 @@ void __init mpc85xx_rdb_pic_init(void)
 
BUG_ON(mpic == NULL);
mpic_init(mpic);
-
-#ifdef CONFIG_QUICC_ENGINE
-   np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
-   if (np) {
-   qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
-   qe_ic_cascade_high_mpic);
-   of_node_put(np);
-
-   } else
-   pr_err("%s: Could not find qe-ic node\n", __func__);
-#endif
-
 }
 
 /*
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c 
b/arch/powerpc/platforms/85xx/twr_p102x.c
index 360f625..6be9b33 100644
--- 

[PATCH v3 5/6] drivers/pci/hotplug: Remove likely() and unlikely() in powernv driver

[Gavin Shan]

This removes likely() and unlikely() in pnv_php.c as the code isn't
running in hot path. Those macros to affect CPU's branch stream don't
help a lot for performance. I used them to identify the cases are
likely or unlikely to happen. No logical changes introduced.

Signed-off-by: Gavin Shan 
---
 drivers/pci/hotplug/pnv_php.c | 56 +--
 1 file changed, 28 insertions(+), 28 deletions(-)

diff --git a/drivers/pci/hotplug/pnv_php.c b/drivers/pci/hotplug/pnv_php.c
index e6245b0..182f218 100644
--- a/drivers/pci/hotplug/pnv_php.c
+++ b/drivers/pci/hotplug/pnv_php.c
@@ -122,7 +122,7 @@ static void pnv_php_detach_device_nodes(struct device_node 
*parent)
 
of_node_put(dn);
refcount = atomic_read(>kobj.kref.refcount);
-   if (unlikely(refcount != 1))
+   if (refcount != 1)
pr_warn("Invalid refcount %d on <%s>\n",
refcount, of_node_full_name(dn));
 
@@ -184,11 +184,11 @@ static int pnv_php_populate_changeset(struct of_changeset 
*ocs,
 
for_each_child_of_node(dn, child) {
ret = of_changeset_attach_node(ocs, child);
-   if (unlikely(ret))
+   if (ret)
break;
 
ret = pnv_php_populate_changeset(ocs, child);
-   if (unlikely(ret))
+   if (ret)
break;
}
 
@@ -201,7 +201,7 @@ static void *pnv_php_add_one_pdn(struct device_node *dn, 
void *data)
struct pci_dn *pdn;
 
pdn = pci_add_device_node_info(hose, dn);
-   if (unlikely(!pdn))
+   if (!pdn)
return ERR_PTR(-ENOMEM);
 
return NULL;
@@ -224,21 +224,21 @@ static int pnv_php_add_devtree(struct pnv_php_slot 
*php_slot)
 * fits the real size.
 */
fdt1 = kzalloc(0x1, GFP_KERNEL);
-   if (unlikely(!fdt1)) {
+   if (!fdt1) {
ret = -ENOMEM;
dev_warn(_slot->pdev->dev, "Cannot alloc FDT blob\n");
goto out;
}
 
ret = pnv_pci_get_device_tree(php_slot->dn->phandle, fdt1, 0x1);
-   if (unlikely(ret)) {
+   if (ret) {
dev_warn(_slot->pdev->dev, "Error %d getting FDT blob\n",
 ret);
goto free_fdt1;
}
 
fdt = kzalloc(fdt_totalsize(fdt1), GFP_KERNEL);
-   if (unlikely(!fdt)) {
+   if (!fdt) {
ret = -ENOMEM;
dev_warn(_slot->pdev->dev, "Cannot %d bytes memory\n",
 fdt_totalsize(fdt1));
@@ -248,7 +248,7 @@ static int pnv_php_add_devtree(struct pnv_php_slot 
*php_slot)
/* Unflatten device tree blob */
memcpy(fdt, fdt1, fdt_totalsize(fdt1));
dt = of_fdt_unflatten_tree(fdt, php_slot->dn, NULL);
-   if (unlikely(!dt)) {
+   if (!dt) {
ret = -EINVAL;
dev_warn(_slot->pdev->dev, "Cannot unflatten FDT\n");
goto free_fdt;
@@ -258,7 +258,7 @@ static int pnv_php_add_devtree(struct pnv_php_slot 
*php_slot)
of_changeset_init(_slot->ocs);
pnv_php_reverse_nodes(php_slot->dn);
ret = pnv_php_populate_changeset(_slot->ocs, php_slot->dn);
-   if (unlikely(ret)) {
+   if (ret) {
pnv_php_reverse_nodes(php_slot->dn);
dev_warn(_slot->pdev->dev, "Error %d populating 
changeset\n",
 ret);
@@ -267,7 +267,7 @@ static int pnv_php_add_devtree(struct pnv_php_slot 
*php_slot)
 
php_slot->dn->child = NULL;
ret = of_changeset_apply(_slot->ocs);
-   if (unlikely(ret)) {
+   if (ret) {
dev_warn(_slot->pdev->dev, "Error %d applying changeset\n",
 ret);
goto destroy_changeset;
@@ -301,7 +301,7 @@ int pnv_php_set_slot_power_state(struct hotplug_slot *slot,
int ret;
 
ret = pnv_pci_set_power_state(php_slot->id, state, );
-   if (likely(ret > 0)) {
+   if (ret > 0) {
if (be64_to_cpu(msg.params[1]) != php_slot->dn->phandle ||
be64_to_cpu(msg.params[2]) != state ||
be64_to_cpu(msg.params[3]) != OPAL_SUCCESS) {
@@ -311,7 +311,7 @@ int pnv_php_set_slot_power_state(struct hotplug_slot *slot,
 be64_to_cpu(msg.params[3]));
return -ENOMSG;
}
-   } else if (unlikely(ret < 0)) {
+   } else if (ret < 0) {
dev_warn(_slot->pdev->dev, "Error %d powering %s\n",
 ret, (state == OPAL_PCI_SLOT_POWER_ON) ? "on" : "off");
return ret;
@@ -338,7 +338,7 @@ static int pnv_php_get_power_state(struct hotplug_slot 
*slot, u8 *state)
 * be on.
 */
ret = pnv_pci_get_power_state(php_slot->id, _state);
-   if (unlikely(ret)) {
+   if (ret) {
  

[PATCH v3 4/6] powerpc/powernv: Unfreeze PE on allocation

[Gavin Shan]

This unfreezes PE when it's initialized because the PE might be put
into frozen state in the last hot remove path. It's not harmful to
do so if the PE is already in unfrozen state.

Signed-off-by: Gavin Shan 
---
 arch/powerpc/platforms/powernv/pci-ioda.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c 
b/arch/powerpc/platforms/powernv/pci-ioda.c
index 38a5c65..841395e 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -133,9 +133,21 @@ static inline bool pnv_pci_is_m64_flags(unsigned long 
resource_flags)
 
 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
 {
+   s64 rc;
+
phb->ioda.pe_array[pe_no].phb = phb;
phb->ioda.pe_array[pe_no].pe_number = pe_no;
 
+   /* Clear the PE frozen state as it might be put into frozen state
+* in the last PCI remove path. It's not harmful to do so when the
+* PE is already in unfrozen state.
+*/
+   rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
+  OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
+   if (rc != OPAL_SUCCESS)
+   pr_warn("%s: Error %lld unfreezing PHB#%d-PE#%d\n",
+   __func__, rc, phb->hose->global_number, pe_no);
+
return >ioda.pe_array[pe_no];
 }
 
-- 
2.1.0

Pull request: scottwood/linux.git next

[Scott Wood]

Highlights include qbman support (a prerequisite for datapath drivers
such as ethernet), a PCI DMA fix+improvement, reset handler changes, more
8xx optimizations, and some cleanups and fixes.

The following changes since commit f1a55ce0544251746d9b52fb85ad32f31a43fbd2:

  powerpc: Clean up tm_abort duplication in hash_utils_64.c (2016-09-23 
07:54:23 +1000)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git next

for you to fetch changes up to e0b80f00bb96b925995d53980e0c764430bedb42:

  arch/powerpc: Add CONFIG_FSL_DPAA to corenetXX_smp_defconfig (2016-09-25 
02:39:01 -0500)


Andrey Smirnov (6):
  powerpc/mpc85xx_mds: Select PHYLIB only if NETDEVICES is enabled
  powerpc/e8248e: Select PHYLIB only if NETDEVICES is enabled
  powerpc/sgy_cts1000: Fix gpio_halt_cb()'s signature
  powerpc: Factor out common code in setup-common.c
  powerpc: Call chained reset handlers during reset
  powerpc: Convert fsl_rstcr_restart to a reset handler

Christophe Leroy (9):
  powerpc32: Use instruction symbolic names in check_io_access()
  soc/fsl/qe: fix Oops on CPM1 (and likely CPM2)
  powerpc/8xx: use SPRN_EIE and SPRN_EID to enable/disable interrupts
  powerpc/8xx: add system_reset_exception
  powerpc/8xx: add dedicated machine check handler
  soc/fsl/qe: fix gpio save_regs functions
  powerpc/8xx: use r3 to scratch CR in ITLBmiss
  powerpc/8xx: Move additional DTLBMiss handlers out of exception area
  powerpc/8xx: make user addr DTLB miss the short path

Claudiu Manoil (5):
  soc/fsl: Introduce DPAA 1.x BMan device driver
  soc/fsl: Introduce DPAA 1.x QMan device driver
  soc/bman: Add self-test for BMan driver
  soc/qman: Add self-test for QMan driver
  arch/powerpc: Add CONFIG_FSL_DPAA to corenetXX_smp_defconfig

Julia Lawall (2):
  fsl/qe: use of_property_read_bool
  powerpc/mpic: use of_property_read_bool

Kevin Hao (1):
  powerpc/83xx: factor out the common codes of setup arch functions

Scott Wood (1):
  powerpc/fsl_pci: Size upper inbound window based on RAM size

Vaishali Thakkar (1):
  soc/fsl/qe: Use resource_size

Zhao Qiang (1):
  soc/fsl/qe: Use of_adress_to_resource() in get_qe_base()

 arch/powerpc/Makefile |4 +-
 arch/powerpc/configs/dpaa.config  |1 +
 arch/powerpc/include/asm/cputable.h   |1 +
 arch/powerpc/include/asm/hw_irq.h |6 +
 arch/powerpc/include/asm/ppc-opcode.h |1 +
 arch/powerpc/include/asm/reg.h|2 +
 arch/powerpc/include/asm/reg_8xx.h|4 +
 arch/powerpc/kernel/cputable.c|1 +
 arch/powerpc/kernel/head_8xx.S|  136 +-
 arch/powerpc/kernel/setup-common.c|   27 +-
 arch/powerpc/kernel/traps.c   |   45 +-
 arch/powerpc/platforms/82xx/Kconfig   |4 +-
 arch/powerpc/platforms/82xx/ep8248e.c |4 +-
 arch/powerpc/platforms/83xx/asp834x.c |4 +-
 arch/powerpc/platforms/83xx/km83xx.c  |5 +-
 arch/powerpc/platforms/83xx/misc.c|8 +
 arch/powerpc/platforms/83xx/mpc830x_rdb.c |5 +-
 arch/powerpc/platforms/83xx/mpc831x_rdb.c |5 +-
 arch/powerpc/platforms/83xx/mpc832x_mds.c |5 +-
 arch/powerpc/platforms/83xx/mpc832x_rdb.c |5 +-
 arch/powerpc/platforms/83xx/mpc834x_itx.c |5 +-
 arch/powerpc/platforms/83xx/mpc834x_mds.c |5 +-
 arch/powerpc/platforms/83xx/mpc836x_mds.c |5 +-
 arch/powerpc/platforms/83xx/mpc836x_rdk.c |5 +-
 arch/powerpc/platforms/83xx/mpc837x_mds.c |5 +-
 arch/powerpc/platforms/83xx/mpc837x_rdb.c |5 +-
 arch/powerpc/platforms/83xx/mpc83xx.h |1 +
 arch/powerpc/platforms/83xx/sbc834x.c |5 +-
 arch/powerpc/platforms/85xx/Kconfig   |2 +-
 arch/powerpc/platforms/85xx/bsc913x_qds.c |1 -
 arch/powerpc/platforms/85xx/bsc913x_rdb.c |1 -
 arch/powerpc/platforms/85xx/c293pcie.c|1 -
 arch/powerpc/platforms/85xx/corenet_generic.c |1 -
 arch/powerpc/platforms/85xx/ge_imp3a.c|1 -
 arch/powerpc/platforms/85xx/mpc8536_ds.c  |1 -
 arch/powerpc/platforms/85xx/mpc85xx_ads.c |1 -
 arch/powerpc/platforms/85xx/mpc85xx_cds.c |   25 +-
 arch/powerpc/platforms/85xx/mpc85xx_ds.c  |3 -
 arch/powerpc/platforms/85xx/mpc85xx_mds.c |   12 +-
 arch/powerpc/platforms/85xx/mpc85xx_rdb.c |   10 -
 arch/powerpc/platforms/85xx/mvme2500.c|1 -
 arch/powerpc/platforms/85xx/p1010rdb.c|1 -
 arch/powerpc/platforms/85xx/p1022_ds.c|1 -
 arch/powerpc/platforms/85xx/p1022_rdk.c   |1 -
 arch/powerpc/platforms/85xx/p1023_rdb.c   |1 -
 arch/powerpc/platforms/85xx/ppa8548.c |1 -
 arch/powerpc/platforms/85xx/qemu_e500.c   |  

Re: [bug] crypto/vmx/p8_ghash memory corruption in 4.8-rc7

[Herbert Xu]

On Tue, Sep 27, 2016 at 05:01:03AM -0400, Jan Stancek wrote:
> 
> Also, does that mean that padlock_sha has similar problem?
> It does not seem to reserve any space for fallback __ctx and it calls
> init()/update()/export() with padlock_sha_desc's fallback:
> 
> struct padlock_sha_desc {
> struct shash_desc fallback;
> };
> 
> static struct shash_alg sha1_alg = {
> .descsize   =   sizeof(struct padlock_sha_desc),

Actually I was wrong when I said that the API couldn't handle
a dynamic fallback.  It can and padlock-sha does the right thing
by updating descsize in the cra_init function.

So this is what vmx should do too.

Thanks,
-- 
Email: Herbert Xu 
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

Re: [bug] crypto/vmx/p8_ghash memory corruption in 4.8-rc7

[Herbert Xu]

On Tue, Sep 27, 2016 at 04:46:44PM -0300, Marcelo Cerri wrote:
> 
> Can you check if the problem occurs with this patch?

In light of the fact that padlock-sha is the correct example
to follow, you only need to add one line to the init_tfm fucntion
to update the descsize based on that of the fallback.

Thanks,
-- 
Email: Herbert Xu 
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

Re: [PATCH] PCI: Add parameter @mmio_force_on to pci_update_resource()

[Gavin Shan]

On Wed, Sep 28, 2016 at 10:06:44AM +1000, Benjamin Herrenschmidt wrote:
>On Wed, 2016-09-28 at 09:37 +1000, Gavin Shan wrote:
>> 
>> Yeah, it's safe to update it with memory decoding on. As the function call
>> flow I listed in the changelog (as below), nobody should access the IOV BAR
>> when pci_update_resource() is called. However, the PF's memory BARs might
>> be accessed that time and it's not safe to disable PF's memory decoding.
>
>The problem isn't so much whether anybody accesses the IOV BAR while
>it's updated but whether the IOV BAR will decode at all.
>
>IE. The BAR is updated in two steps, 32-bit each. That means that there
>is a window where it contains a "bogus" value.
>
>If that bogus value conflicts with another BAR (another BAR of the  PF
>or another PF of the same device for example) then there is a risk of
>something bad happening if the driver accesses that conflicting
>resource during that window.
>
>On the other hand, if the IOV BAR doesn't decode at all while the
>update is done, which I think is the case as I believe SR-IOV isn't
>enabled during the update (please verify), then we are safe.
>

I assumed the SRIOV and its memory space aren't enabled when updating IOV
BARs, but unfortunately they have been enabled at that point. I think
pcibios_sriov_enable() should be moved before SRIOV is enabled. Note
that pcibios_sriov_enable() is used by PowerNV only.

static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
{
:
pci_iov_set_numvfs(dev, nr_virtfn);
iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
pci_cfg_access_lock(dev);
pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);   
/* SRIOV and its memory space enabled */
msleep(100);
pci_cfg_access_unlock(dev);

iov->initial_VFs = initial;
if (nr_virtfn < initial)
initial = nr_virtfn;

rc = pcibios_sriov_enable(dev, initial);
/* IOV BARs are updated inside it */

:
}

Thanks,
Gavin

>Cheers,
>Ben.
>

Re: [PATCH] Fix "ibm,processor-radix-AP-encodings"

[Aneesh Kumar K.V]

Balbir Singh  writes:

> The top 3 bits of the lower order byte should contain the
> AP encoding, we assume the top 3 bits of the MSB.


Are you sure, Power architecture documents always confuse about MSB vs
lowe order bytes. ?

>
> Signed-off-by: Balbir Singh 
> ---
>
>  - Detected while reviewing Chris Smart's patch to add radix-AP-encoding
>to skiboot
>  - Also fixed typo (sift/shift)
>
>  arch/powerpc/mm/pgtable-radix.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c
> index af897d9..d525b0b 100644
> --- a/arch/powerpc/mm/pgtable-radix.c
> +++ b/arch/powerpc/mm/pgtable-radix.c
> @@ -245,10 +245,10 @@ static int __init radix_dt_scan_page_sizes(unsigned 
> long node,
>
>   struct mmu_psize_def *def;
>
> - /* top 3 bit is AP encoding */
> - shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
> - ap = be32_to_cpu(prop[0]) >> 29;
> - pr_info("Page size sift = %d AP=0x%x\n", shift, ap);
> + /* top 3 bits of the lower order byte is AP encoding */
> + shift = be32_to_cpu(prop[0]) & 0x1f;
> + ap = (be32_to_cpu(prop[0]) >> 5) & 0x7;
> + pr_info("Page size shift = %d AP=0x%x\n", shift, ap);
>
>   idx = get_idx_from_shift(shift);
>   if (idx < 0)

-aneesh

Re: [PATCH] PCI: Add parameter @mmio_force_on to pci_update_resource()

[Benjamin Herrenschmidt]

On Wed, 2016-09-28 at 09:37 +1000, Gavin Shan wrote:
> 
> Yeah, it's safe to update it with memory decoding on. As the function call
> flow I listed in the changelog (as below), nobody should access the IOV BAR
> when pci_update_resource() is called. However, the PF's memory BARs might
> be accessed that time and it's not safe to disable PF's memory decoding.

The problem isn't so much whether anybody accesses the IOV BAR while
it's updated but whether the IOV BAR will decode at all.

IE. The BAR is updated in two steps, 32-bit each. That means that there
is a window where it contains a "bogus" value.

If that bogus value conflicts with another BAR (another BAR of the  PF
or another PF of the same device for example) then there is a risk of
something bad happening if the driver accesses that conflicting
resource during that window.

On the other hand, if the IOV BAR doesn't decode at all while the
update is done, which I think is the case as I believe SR-IOV isn't
enabled during the update (please verify), then we are safe.

Cheers,
Ben.

Re: [PATCH v5] powerpc: Do not make the entire heap executable

[Michael Ellerman]

Denys Vlasenko  writes:

> On 32-bit powerpc the ELF PLT sections of binaries (built with --bss-plt,
> or with a toolchain which defaults to it) look like this:

Or (it seems), for all programs built with -pg (profiling).

>   [17] .sbss NOBITS  0002aff8 01aff8 14 00  WA  0   0 
>  4
>   [18] .plt  NOBITS  0002b00c 01aff8 84 00 WAX  0   0 
>  4
>   [19] .bss  NOBITS  0002b090 01aff8 a4 00  WA  0   0 
>  4
>
> Which results in an ELF load header:
>
>   Type   Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
>   LOAD   0x019c70 0x00029c70 0x00029c70 0x01388 0x014c4 RWE 0x1
>
> This is all correct, the load region containing the PLT is marked as
> executable. Note that the PLT starts at 0002b00c but the file mapping ends at
> 0002aff8, so the PLT falls in the 0 fill section described by the load header,
> and after a page boundary.
>
> Unfortunately the generic ELF loader ignores the X bit in the load headers
> when it creates the 0 filled non-file backed mappings. It assumes all of these
> mappings are RW BSS sections, which is not the case for PPC.
>
> gcc/ld has an option (--secure-plt) to not do this, this is said to incur
> a small performance penalty.
>
> Currently, to support 32-bit binaries with PLT in BSS kernel maps *entire
> brk area* with executable rights for all binaries, even --secure-plt ones.
>
> Stop doing that.
>
> Teach the ELF loader to check the X bit in the relevant load header
> and create 0 filled anonymous mappings that are executable
> if the load header requests that.
...
>
> Signed-off-by: Jason Gunthorpe 
> Signed-off-by: Denys Vlasenko 
> Reviewed-by: Kees Cook 
> CC: Michael Ellerman 

This looks OK to me, I've tested it with --bss-plt and --secure-plt and
also -pg.

So for the powerpc part I'll give you an:

Acked-by: Michael Ellerman 

But this is not really a powerpc patch, and I'm not an ELF expert. So
I'm not comfortable merging it via the powerpc tree. It doesn't look
like we really have a maintainer for binfmt_elf.c, so I'm not sure who
should be acking that part.

I've added Al Viro to Cc, he maintains fs/ and might be interested.

I've also added Andrew Morton who might be happy to put this in his
tree, and see if anyone complains?

Also here: https://patchwork.ozlabs.org/patch/661595/

cheers

> ---
> Changes since v4:
> * if (current->personality & READ_IMPLIES_EXEC), still use VM_EXEC
>   for 32-bit executables.
>
> Changes since v3:
> * typo fix in commit message
> * rebased to current Linus tree
>
> Changes since v2:
> * moved capability to map with VM_EXEC into vm_brk_flags()
>
> Changes since v1:
> * wrapped lines to not exceed 79 chars
> * improved comment
> * expanded CC list
>
>  arch/powerpc/include/asm/page.h |  3 ++-
>  fs/binfmt_elf.c | 30 ++
>  include/linux/mm.h  |  1 +
>  mm/mmap.c   | 21 -
>  4 files changed, 41 insertions(+), 14 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
> index 56398e7..d188f51 100644
> --- a/arch/powerpc/include/asm/page.h
> +++ b/arch/powerpc/include/asm/page.h
> @@ -230,7 +230,9 @@ extern long long virt_phys_offset;
>   * and needs to be executable.  This means the whole heap ends
>   * up being executable.
>   */
> -#define VM_DATA_DEFAULT_FLAGS32  (VM_READ | VM_WRITE | VM_EXEC | \
> +#define VM_DATA_DEFAULT_FLAGS32 \
> + (((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \
> +  VM_READ | VM_WRITE | \
>VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
>  
>  #define VM_DATA_DEFAULT_FLAGS64  (VM_READ | VM_WRITE | \
> diff --git a/fs/binfmt_elf.c b/fs/binfmt_elf.c
> index 7f6aff3f..2b57b5a 100644
> --- a/fs/binfmt_elf.c
> +++ b/fs/binfmt_elf.c
> @@ -91,12 +91,18 @@ static struct linux_binfmt elf_format = {
>  
>  #define BAD_ADDR(x) ((unsigned long)(x) >= TASK_SIZE)
>  
> -static int set_brk(unsigned long start, unsigned long end)
> +static int set_brk(unsigned long start, unsigned long end, int prot)
>  {
>   start = ELF_PAGEALIGN(start);
>   end = ELF_PAGEALIGN(end);
>   if (end > start) {
> - int error = vm_brk(start, end - start);
> + /*
> +  * Map the last of the bss segment.
> +  * If the header is requesting these pages to be
> +  * executable, honour that (ppc32 needs this).
> +  */
> + int error = vm_brk_flags(start, end - start,
> + prot & PROT_EXEC ? VM_EXEC : 0);
>   if (error)
>   return error;
>   }
> @@ -524,6 +530,7 @@ static unsigned long load_elf_interp(struct elfhdr 
> *interp_elf_ex,
>   unsigned 

Re: [PATCH] PCI: Add parameter @mmio_force_on to pci_update_resource()

[Bjorn Helgaas]

Hi Gavin,

On Mon, Sep 19, 2016 at 09:53:30AM +1000, Gavin Shan wrote:
> In pci_update_resource(), the PCI device's memory decoding (0x2 in
> PCI_COMMAND) is disabled when 64-bits memory BAR is updated if the
> PCI device's memory space wasn't asked to be always on by @pdev->
> mmio_always_on. The PF's memory decoding might be disabled when
> updating its IOV BARs in the following path. Actually, the PF's
> memory decoding shouldn't be disabled in this scenario as the PF
> has been started to provide services:

The reason we disable memory decoding while updating a 64-bit BAR is
because we can't do the update atomically, and a half-updated BAR might
conflict with other devices.

You need to explain what is special about these SR-IOV BARs that makes it
safe to update them non-atomically while decoding is enabled.

>sriov_numvfs_store
>pdev->driver->sriov_configure
>mlx5_core_sriov_configure
>pci_enable_sriov
>sriov_enable
>pcibios_sriov_enable
>pnv_pci_sriov_enable
>pnv_pci_vf_resource_shift
>pci_update_resource
> 
> This doesn't change the PF's memory decoding in the path by introducing
> additional parameter (@mmio_force_on) to pci_update_resource().
> 
> Reported-by: Carol Soto 
> Signed-off-by: Gavin Shan 
> Tested-by: Carol Soto 
> ---
>  arch/powerpc/platforms/powernv/pci-ioda.c | 2 +-
>  drivers/pci/iov.c | 2 +-
>  drivers/pci/pci.c | 2 +-
>  drivers/pci/setup-res.c   | 9 +
>  include/linux/pci.h   | 2 +-
>  5 files changed, 9 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c 
> b/arch/powerpc/platforms/powernv/pci-ioda.c
> index bc0c91e..2d6a2b7 100644
> --- a/arch/powerpc/platforms/powernv/pci-ioda.c
> +++ b/arch/powerpc/platforms/powernv/pci-ioda.c
> @@ -999,7 +999,7 @@ static int pnv_pci_vf_resource_shift(struct pci_dev *dev, 
> int offset)
>   dev_info(>dev, "VF BAR%d: %pR shifted to %pR (%sabling %d 
> VFs shifted by %d)\n",
>i, , res, (offset > 0) ? "En" : "Dis",
>num_vfs, offset);
> - pci_update_resource(dev, i + PCI_IOV_RESOURCES);
> + pci_update_resource(dev, i + PCI_IOV_RESOURCES, true);
>   }
>   return 0;
>  }
> diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
> index 2194b44..117aae6 100644
> --- a/drivers/pci/iov.c
> +++ b/drivers/pci/iov.c
> @@ -511,7 +511,7 @@ static void sriov_restore_state(struct pci_dev *dev)
>   return;
>  
>   for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++)
> - pci_update_resource(dev, i);
> + pci_update_resource(dev, i, false);
>  
>   pci_write_config_dword(dev, iov->pos + PCI_SRIOV_SYS_PGSIZE, iov->pgsz);
>   pci_iov_set_numvfs(dev, iov->num_VFs);
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index aab9d51..87a33c0 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -545,7 +545,7 @@ static void pci_restore_bars(struct pci_dev *dev)
>   return;
>  
>   for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
> - pci_update_resource(dev, i);
> + pci_update_resource(dev, i, false);
>  }
>  
>  static const struct pci_platform_pm_ops *pci_platform_pm;
> diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
> index 66c4d8f..e8a50ff 100644
> --- a/drivers/pci/setup-res.c
> +++ b/drivers/pci/setup-res.c
> @@ -26,7 +26,7 @@
>  #include "pci.h"
>  
>  
> -void pci_update_resource(struct pci_dev *dev, int resno)
> +void pci_update_resource(struct pci_dev *dev, int resno, bool mmio_force_on)
>  {
>   struct pci_bus_region region;
>   bool disable;
> @@ -81,7 +81,8 @@ void pci_update_resource(struct pci_dev *dev, int resno)
>* disable decoding so that a half-updated BAR won't conflict
>* with another device.
>*/
> - disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
> + disable = (res->flags & IORESOURCE_MEM_64) &&
> +   !mmio_force_on && !dev->mmio_always_on;
>   if (disable) {
>   pci_read_config_word(dev, PCI_COMMAND, );
>   pci_write_config_word(dev, PCI_COMMAND,
> @@ -310,7 +311,7 @@ int pci_assign_resource(struct pci_dev *dev, int resno)
>   res->flags &= ~IORESOURCE_STARTALIGN;
>   dev_info(>dev, "BAR %d: assigned %pR\n", resno, res);
>   if (resno < PCI_BRIDGE_RESOURCES)
> - pci_update_resource(dev, resno);
> + pci_update_resource(dev, resno, false);
>  
>   return 0;
>  }
> @@ -350,7 +351,7 @@ int pci_reassign_resource(struct pci_dev *dev, int resno, 
> resource_size_t addsiz
>   dev_info(>dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
>resno, res, (unsigned long long) addsize);
>   if (resno < PCI_BRIDGE_RESOURCES)
> - pci_update_resource(dev, 

[PATCH] usb: Convert pr_warning to pr_warn

[Joe Perches]

Use the more common logging mechanism.

Miscellanea:

o Realign multiline statements
o Coalesce format

Signed-off-by: Joe Perches 
---
 drivers/usb/gadget/function/rndis.c |  9 -
 drivers/usb/gadget/function/u_serial.c  |  4 ++--
 drivers/usb/gadget/udc/at91_udc.h   |  2 +-
 drivers/usb/gadget/udc/atmel_usba_udc.c |  4 ++--
 drivers/usb/gadget/udc/fsl_usb2_udc.h   |  2 +-
 drivers/usb/gadget/udc/m66592-udc.c |  4 ++--
 drivers/usb/gadget/udc/omap_udc.h   |  2 +-
 drivers/usb/gadget/udc/pxa25x_udc.h |  2 +-
 drivers/usb/host/isp1362-hcd.c  | 27 ++-
 drivers/usb/isp1760/isp1760-if.c|  2 +-
 10 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/drivers/usb/gadget/function/rndis.c 
b/drivers/usb/gadget/function/rndis.c
index ab6ac1b74ac0..766c328c15c0 100644
--- a/drivers/usb/gadget/function/rndis.c
+++ b/drivers/usb/gadget/function/rndis.c
@@ -474,8 +474,7 @@ static int gen_ndis_query_resp(struct rndis_params *params, 
u32 OID, u8 *buf,
break;
 
default:
-   pr_warning("%s: query unknown OID 0x%08X\n",
-__func__, OID);
+   pr_warn("%s: query unknown OID 0x%08X\n", __func__, OID);
}
if (retval < 0)
length = 0;
@@ -546,8 +545,8 @@ static int gen_ndis_set_resp(struct rndis_params *params, 
u32 OID,
break;
 
default:
-   pr_warning("%s: set unknown OID 0x%08X, size %d\n",
-__func__, OID, buf_len);
+   pr_warn("%s: set unknown OID 0x%08X, size %d\n",
+   __func__, OID, buf_len);
}
 
return retval;
@@ -854,7 +853,7 @@ int rndis_msg_parser(struct rndis_params *params, u8 *buf)
 * In one case those messages seemed to relate to the host
 * suspending itself.
 */
-   pr_warning("%s: unknown RNDIS message 0x%08X len %d\n",
+   pr_warn("%s: unknown RNDIS message 0x%08X len %d\n",
__func__, MsgType, MsgLength);
print_hex_dump_bytes(__func__, DUMP_PREFIX_OFFSET,
 buf, MsgLength);
diff --git a/drivers/usb/gadget/function/u_serial.c 
b/drivers/usb/gadget/function/u_serial.c
index e0cd1e4c8892..62ec842874aa 100644
--- a/drivers/usb/gadget/function/u_serial.c
+++ b/drivers/usb/gadget/function/u_serial.c
@@ -622,8 +622,8 @@ static void gs_write_complete(struct usb_ep *ep, struct 
usb_request *req)
switch (req->status) {
default:
/* presumably a transient fault */
-   pr_warning("%s: unexpected %s status %d\n",
-   __func__, ep->name, req->status);
+   pr_warn("%s: unexpected %s status %d\n",
+   __func__, ep->name, req->status);
/* FALL THROUGH */
case 0:
/* normal completion */
diff --git a/drivers/usb/gadget/udc/at91_udc.h 
b/drivers/usb/gadget/udc/at91_udc.h
index 0a433e6b346b..9bbe72764f31 100644
--- a/drivers/usb/gadget/udc/at91_udc.h
+++ b/drivers/usb/gadget/udc/at91_udc.h
@@ -175,7 +175,7 @@ struct at91_request {
 #endif
 
 #define ERR(stuff...)  pr_err("udc: " stuff)
-#define WARNING(stuff...)  pr_warning("udc: " stuff)
+#define WARNING(stuff...)  pr_warn("udc: " stuff)
 #define INFO(stuff...) pr_info("udc: " stuff)
 #define DBG(stuff...)  pr_debug("udc: " stuff)
 
diff --git a/drivers/usb/gadget/udc/atmel_usba_udc.c 
b/drivers/usb/gadget/udc/atmel_usba_udc.c
index 45bc997d0711..1ef7a9a9d7f5 100644
--- a/drivers/usb/gadget/udc/atmel_usba_udc.c
+++ b/drivers/usb/gadget/udc/atmel_usba_udc.c
@@ -1464,8 +1464,8 @@ static void usba_control_irq(struct usba_udc *udc, struct 
usba_ep *ep)
pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
DBG(DBG_HW, "Packet length: %u\n", pkt_len);
if (pkt_len != sizeof(crq)) {
-   pr_warning("udc: Invalid packet length %u "
-   "(expected %zu)\n", pkt_len, sizeof(crq));
+   pr_warn("udc: Invalid packet length %u (expected 
%zu)\n",
+   pkt_len, sizeof(crq));
set_protocol_stall(udc, ep);
return;
}
diff --git a/drivers/usb/gadget/udc/fsl_usb2_udc.h 
b/drivers/usb/gadget/udc/fsl_usb2_udc.h
index 84715625b2b3..e92b8408b6f6 100644
--- a/drivers/usb/gadget/udc/fsl_usb2_udc.h
+++ b/drivers/usb/gadget/udc/fsl_usb2_udc.h
@@ -554,7 +554,7 @@ static void dump_msg(const char *label, const u8 * buf, 
unsigned int length)
 #endif
 
 #define ERR(stuff...)  pr_err("udc: " stuff)
-#define WARNING(stuff...)  pr_warning("udc: " stuff)
+#define WARNING(stuff...)  pr_warn("udc: " stuff)
 #define INFO(stuff...) pr_info("udc: " stuff)
 
 

Re: [PATCH] usb: Convert pr_warning to pr_warn

[Robert Jarzmik]

Joe Perches  writes:

> Use the more common logging mechanism.
>
> Miscellanea:
>
> o Realign multiline statements
> o Coalesce format
>
> Signed-off-by: Joe Perches 
For pxa25x_udc.h:
Acked-by: Robert Jarzmik 

Cheers.

--
Robert

Re: [PATCH v7 0/6] perf annotate: Cross arch support + few fixes

[Ravi Bangoria]

Hello,

Any updates?

Arnaldo, if patches looks good to you, can you please pickup them.

-Ravi

On Wednesday 21 September 2016 09:17 PM, Ravi Bangoria wrote:
> Currently Perf annotate support code navigation (branches and calls)
> only when run on the same architecture where perf.data was recorded.
> But, for example, record on powerpc server and annotate on client's
> x86 desktop is not supported.
>
> This patchset adds supports for that.
>
> Example:
>
>   Record on powerpc:
>   $ ./perf record -a
>
>   Report -> Annotate on x86:
>   $ ./perf report -i perf.data.powerpc --vmlinux vmlinux.powerpc
>
> Changes in v7:
>   - Using string for normalized arch names instread of macros.(i.e.
> removed patch 1/7 of v6)
>   - In patch 1/6, make norm_arch as global var instead of passing them
> to each parser.
>   - In patch 1/6 and 6/6, little bit change in initializing instruction
> list.
>   - patch 4/7 of v6 is already accepted. Removed that in v7.
>   - Address other review comments.
>   - Added more examples in patch descriptions.
>
> v6 link:
>   https://lkml.org/lkml/2016/8/19/411
>
> Kim, I don't have arm test machine. Can you please help me to test
> this on arm.
>
>
> Kim Phillips (1):
>   perf annotate: cross arch annotate support fixes for ARM
>
> Naveen N. Rao (1):
>   perf annotate: Add support for powerpc
>
> Ravi Bangoria (4):
>   perf annotate: Add cross arch annotate support
>   perf annotate: Show raw form for jump instruction with indirect target
>   perf annotate: Support jump instruction with target as second operand
>   perf annotate: Fix jump target outside of function address range
>
>  tools/perf/builtin-top.c  |   2 +-
>  tools/perf/ui/browsers/annotate.c |   8 +-
>  tools/perf/ui/gtk/annotate.c  |   2 +-
>  tools/perf/util/annotate.c| 259 
> --
>  tools/perf/util/annotate.h|   8 +-
>  5 files changed, 232 insertions(+), 47 deletions(-)
>

Re: Kernel Oops on 4.8.0-rc8 while running trinity tests

[Abdul Haleem]

The kernel oops is still reproducible on 4.8.0-rc8 on PowerPC bare metal

While running trinity system call fuzzer, I see these kernel oops messages:

Unable to handle kernel paging request for data at address 
0xe45f7702

Faulting instruction address: 0xc0055380
Oops: Kernel access of bad area, sig: 11 [#1]
SMP NR_CPUS=32 NUMA PowerNV
Modules linked in: torture leds_powernv led_class powernv_op_panel 
powernv_rng rng_core autofs4 [last unloaded: rcutorture]

CPU: 28 PID: 19687 Comm: trinity-main Not tainted 4.8.0-rc8-autotest #1
task: c007dc61c600 task.stack: c007ddb2
NIP: c0055380 LR: c0234968 CTR: 
REGS: c007ddb23640 TRAP: 0300   Not tainted (4.8.0-rc8-autotest)
MSR: 90009033   CR: 24002442  XER: 


CFAR: c00087d0 DAR: e45f7702 DSISR: 4000 SOFTE: 1
GPR00: 0007 c007ddb238c0 c0f7c100 c000
GPR04:  0009  
GPR08: e45f7702  007f 0015
GPR12:  c000  1000
GPR16: 0001  c2e02798 10034120
GPR20: 10034108 c007ddf842e0 c0ff0df8 
GPR24: c1fff7ff  c007ddb23a60 0100
GPR28: 0100 c2e02400 c2e02464 
NIP [c0055380] __find_linux_pte_or_hugepte+0x1c0/0x330
LR [c0234968] __unmap_hugepage_range+0x178/0x670
Call Trace:
[c007ddb23980] [c0234e80] __unmap_hugepage_range_final+0x20/0x50
[c007ddb239b0] [c020a52c] unmap_single_vma+0xcc/0x120
[c007ddb239f0] [c020a984] unmap_vmas+0x84/0x120
[c007ddb23a40] [c0212c00] unmap_region+0xd0/0x1a0
[c007ddb23b30] [c0214e8c] do_munmap+0x2dc/0x4a0
[c007ddb23ba0] [c0216800] mmap_region+0x1c0/0x6e0
[c007ddb23c90] [c02170fc] do_mmap+0x3dc/0x4c0
[c007ddb23d20] [c01f1034] vm_mmap_pgoff+0xc4/0x100
[c007ddb23d90] [c02144d0] SyS_mmap_pgoff+0x100/0x2a0
[c007ddb23e10] [c0012424] sys_mmap+0x44/0x70
[c007ddb23e30] [c00095e0] system_call+0x38/0x108
Instruction dump:
7d290030 79081764 3929 3860 7d2a07b4 7c895c36 7d494838 78630044
7908f5e6 79291f24 7d081b78 796b0020 <7d49402a> 7c694214 2eaa f941ffd0
---[ end trace f4f25c6801290199 ]---


On Friday 26 August 2016 12:02 PM, Abdul Haleem wrote:

Hi,

Trinity tests failed on mainline4.8.0-rc3with the following error 
message:


Machine Type : PowerPC Bare Metal & also reproducible on PowerVM LPAR
config : attached

06:05:25 20:36:07 INFO | Test: running trinity tests
06:05:25 20:36:07 INFO | trinity
06:05:25 20:36:07 INFO | STARTtrinity trinity
timestamp=1471912567localtime=Aug 22 20:36:07
06:06:19 Unable to handle kernel paging request for data at address 
0xe475e1dc0700

06:06:19 Faulting instruction address: 0xc00553a0
06:06:19 Oops: Kernel access of bad area, sig: 11 [#1]
06:06:19 SMP NR_CPUS=32 NUMA PowerNV
06:06:19 Modules linked in: torture iptable_mangle ipt_MASQUERADE 
nf_nat_masquerade_ipv4 iptable_nat nf_nat_ipv4 nf_nat 
nf_conntrack_ipv4 nf_defrag_ipv4 xt_conntrack nf_conntrack ipt_REJECT 
nf_reject_ipv4 xt_tcpudp tun bridge stp llc iptable_filter ip_tables 
x_tables binfmt_misc kvm_hv kvm leds_powernv led_class 
powernv_op_panel powernv_rng rng_core autofs4 btrfs xor raid6_pq [last 
unloaded: rcutorture]
06:06:19 CPU: 24 PID: 16309 Comm: trinity-main Not tainted 
4.8.0-rc3-autotest #1

06:06:19 task: c007de33 task.stack: c007d85dc000
06:06:19 NIP: c00553a0 LR: c02345a8 CTR: 
06:06:19 REGS: c007d85df640 TRAP: 0300   Not tainted 
(4.8.0-rc3-autotest)
06:06:19 MSR: 90009033   CR: 
24002452  XER: 
06:06:19 CFAR: c00087d0 DAR: e475e1dc0700 DSISR: 4000 
SOFTE: 1
06:06:19 GPR00: 0007 c007d85df8c0 c0f7ad00 
c000
06:06:19 GPR04:  0009 0700 

06:06:19 GPR08: e475e1dc0700  007f 
0015
06:06:19 GPR12:  cfffe000  
1000
06:06:19 GPR16: 0001  c007ddfa6798 
100341e0
06:06:19 GPR20: 100341c8 c007dc336508 c0ff0df8 

06:06:19 GPR24: c1fff7ff  c007d85dfa60 
0100
06:06:19 GPR28: 0100 c007ddfa6400 c007ddfa6464 
0007

06:06:19 NIP [c00553a0] __find_linux_pte_or_hugepte+0x1c0/0x330
06:06:19 LR [c02345a8] __unmap_hugepage_range+0x178/0x670
06:06:19 Call Trace:
06:06:19 [c007d85df980] [c0234ac0] 
__unmap_hugepage_range_final+0x20/0x50
06:06:19 

Re: [PATCH 5/6] powerpc/boot: add xz support to the wrapper script

[Michael Ellerman]

Oliver O'Halloran  writes:

> This modifies the script so that the -Z option takes an argument to
> specify the compression type. It can either be 'gz', 'xz' or 'none'.
> The legazy --no-gzip and -z options are still supported and will set
> the compression to none and gzip respectively, but they are not
> documented.
>
> Only xz -6 is used for compression rather than xz -9. Using compression
> levels higher than 6 requires the decompressor to build a large (64MB)
> dictionary when decompressing and some environments cannot satisfy large
> allocations (e.g. POWER 6 LPAR partition firmware).

This isn't working for me on machines that use uImage.

That's the "uboot" case in wrapper, where we do:

${MKIMAGE} -A ppc -O linux -T kernel -C gzip -a $membase -e $membase \
$uboot_version -d "$vmz" "$ofile"

ie. we tell mkimage that we're using gzip compression, regardless of
whether we actually are.

That leads to something like:

  ## Booting kernel from Legacy Image at 0100 ...
 Image Name:   Linux-4.8.0-rc5-compiler_gcc-6.2
 Image Type:   PowerPC Linux Kernel Image (gzip compressed)
 Data Size:3381044 Bytes = 3.2 MiB
 Load Address: 
 Entry Point:  
 Verifying Checksum ... OK
  ## Flattened Device Tree blob at 0c00
 Booting using the fdt blob at 0xc00
 Uncompressing Kernel Image ... Error: Bad gzipped data
  gzip compressed: uncompress error -1
  Must RESET board to recover


So you'll need to do some juggling so you can pass the right argument
for -C to mkimage.

cheers

Re: [PATCH] Work around for enabling CONFIG_CMDLINE on ppc64le

[Akshay Adiga]

Hi Michael,

Here is the link to the bug raised on launchpad.
https://bugs.launchpad.net/ubuntu/+source/gcc-5/+bug/1628207


On 09/23/2016 09:45 AM, Akshay Adiga wrote:

Hi Michael,

Anton found this bug and raised it against gcc v7.0 and a fix is 
available

 in upstream gcc.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71709

Currently, gcc v5.4.0  and v6.1.1 shipped with Ubuntu 16.04 and 16.10  
respectively,

 are hitting this problem.

I have also raised bug against Ubuntu for fixing gcc for 16.04.

https://bugzilla.linux.ibm.com/show_bug.cgi?id=146668


On 09/22/2016 03:51 PM, Michael Ellerman wrote:

Akshay Adiga  writes:


Observed that boot arguments (passed as CONFIG_CMDLINE)  are not being
picked up by kernel while using gcc-ppc64-linux-gnu v5.4.0 and v6.1.1.
While it works as expected with v5.3.1 .

Found that in init/main.c in  setup_command_line() the pointers 
passed to

strcpy() is messed up.

Hi Akshay,

Thanks for debugging this.


The problem goes away when compiler optimization is restricted to -O1.
diff --git a/init/main.c b/init/main.c
index a8a58e2..4259c42 100644
--- a/init/main.c
+++ b/init/main.c
@@ -358,7 +358,13 @@ static inline void smp_prepare_cpus(unsigned 
int maxcpus) { }

   * parsing is performed in place, and we should allow a component to
   * store reference of name/value for future reference.
   */
-static void __init setup_command_line(char *command_line)
+static void __init
+#ifdef CONFIG_PPC64
+#if  GCC_VERSION > 50301
+__attribute__((optimize("-O1")))
+#endif
+#endif
+setup_command_line(char *command_line)
  {
  saved_command_line =
  memblock_virt_alloc(strlen(boot_command_line) + 1, 0);

But I can't merge that patch.

Our options are one or both of:
  - get GCC fixed and backport the fix to the compilers we care about.
  - blacklist the broken compiler versions.

Is there a GCC bug filed for this?

cheers

Re: [PATCH v21 06/19] perf, tools: Support alias descriptions

[Arnaldo Carvalho de Melo]

Em Thu, Sep 15, 2016 at 03:24:43PM -0700, Sukadev Bhattiprolu escreveu:
> From: Andi Kleen 
> 
> Add support to print alias descriptions in perf list, which
> are taken from the generated event files.
> 
> The sorting code is changed to put the events with descriptions
> at the end. The descriptions are printed as possibly multiple word
> wrapped lines.

So, now I'm trying to reproduce the results below, but I couldn't find a
tarball with those .json files for me to use, can you provide me with
one?

I've put what I have at:

  git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tmp.perf/json

Now testing Jiri's cross compiling patch...


Thanks,

- Arnaldo
 
> Example output:
> 
> % perf list
> ...
>   arith.fpu_div
>[Divide operations executed]
>   arith.fpu_div_active
>[Cycles when divider is busy executing divide operations]
> 
> Signed-off-by: Andi Kleen 
> Signed-off-by: Sukadev Bhattiprolu 
> Acked-by: Jiri Olsa 
> Acked-by: Ingo Molnar 
> ---
> 
> Changelog
>   - Delete a redundant free()
> 
> Changelog[v14]
>   - [Jiri Olsa] Fail, rather than continue if strdup() returns NULL;
> remove unnecessary __maybe_unused.
> ---
>  tools/perf/util/pmu.c | 83 
> +--
>  tools/perf/util/pmu.h |  1 +
>  2 files changed, 68 insertions(+), 16 deletions(-)
> 
> diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
> index c842886..af1a612 100644
> --- a/tools/perf/util/pmu.c
> +++ b/tools/perf/util/pmu.c
> @@ -222,7 +222,7 @@ static int perf_pmu__parse_snapshot(struct perf_pmu_alias 
> *alias,
>  }
>  
>  static int __perf_pmu__new_alias(struct list_head *list, char *dir, char 
> *name,
> -  char *desc __maybe_unused, char *val)
> +  char *desc, char *val)
>  {
>   struct perf_pmu_alias *alias;
>   int ret;
> @@ -255,6 +255,8 @@ static int __perf_pmu__new_alias(struct list_head *list, 
> char *dir, char *name,
>   perf_pmu__parse_snapshot(alias, dir, name);
>   }
>  
> + alias->desc = desc ? strdup(desc) : NULL;
> +
>   list_add_tail(>list, list);
>  
>   return 0;
> @@ -1044,11 +1046,42 @@ static char *format_alias_or(char *buf, int len, 
> struct perf_pmu *pmu,
>   return buf;
>  }
>  
> -static int cmp_string(const void *a, const void *b)
> +struct pair {
> + char *name;
> + char *desc;
> +};
> +
> +static int cmp_pair(const void *a, const void *b)
> +{
> + const struct pair *as = a;
> + const struct pair *bs = b;
> +
> + /* Put extra events last */
> + if (!!as->desc != !!bs->desc)
> + return !!as->desc - !!bs->desc;
> + return strcmp(as->name, bs->name);
> +}
> +
> +static void wordwrap(char *s, int start, int max, int corr)
>  {
> - const char * const *as = a;
> - const char * const *bs = b;
> - return strcmp(*as, *bs);
> + int column = start;
> + int n;
> +
> + while (*s) {
> + int wlen = strcspn(s, " \t");
> +
> + if (column + wlen >= max && column > start) {
> + printf("\n%*s", start, "");
> + column = start + corr;
> + }
> + n = printf("%s%.*s", column > start ? " " : "", wlen, s);
> + if (n <= 0)
> + break;
> + s += wlen;
> + column += n;
> + while (isspace(*s))
> + s++;
> + }
>  }
>  
>  void print_pmu_events(const char *event_glob, bool name_only)
> @@ -1058,7 +1091,9 @@ void print_pmu_events(const char *event_glob, bool 
> name_only)
>   char buf[1024];
>   int printed = 0;
>   int len, j;
> - char **aliases;
> + struct pair *aliases;
> + int numdesc = 0;
> + int columns = 78;
>  
>   pmu = NULL;
>   len = 0;
> @@ -1068,14 +1103,15 @@ void print_pmu_events(const char *event_glob, bool 
> name_only)
>   if (pmu->selectable)
>   len++;
>   }
> - aliases = zalloc(sizeof(char *) * len);
> + aliases = zalloc(sizeof(struct pair) * len);
>   if (!aliases)
>   goto out_enomem;
>   pmu = NULL;
>   j = 0;
>   while ((pmu = perf_pmu__scan(pmu)) != NULL) {
>   list_for_each_entry(alias, >aliases, list) {
> - char *name = format_alias(buf, sizeof(buf), pmu, alias);
> + char *name = alias->desc ? alias->name :
> + format_alias(buf, sizeof(buf), pmu, alias);
>   bool is_cpu = !strcmp(pmu->name, "cpu");
>  
>   if (event_glob != NULL &&
> @@ -1084,12 +1120,19 @@ void print_pmu_events(const char *event_glob, bool 
> name_only)
>  event_glob
>   continue;
>  
> -  

Re: [PATCH v21 06/19] perf, tools: Support alias descriptions

[Sukadev Bhattiprolu]

Arnaldo Carvalho de Melo [a...@kernel.org] wrote:
> Em Thu, Sep 15, 2016 at 03:24:43PM -0700, Sukadev Bhattiprolu escreveu:
> > From: Andi Kleen 
> > 
> > Add support to print alias descriptions in perf list, which
> > are taken from the generated event files.
> > 
> > The sorting code is changed to put the events with descriptions
> > at the end. The descriptions are printed as possibly multiple word
> > wrapped lines.
> 
> So, now I'm trying to reproduce the results below, but I couldn't find a
> tarball with those .json files for me to use, can you provide me with
> one?

The data files are in my github, in the json-code+data-v21 branch
starting with 23bb101. They are individual commits rather than a
tarball though.

>   https://github.com/sukadev/linux.git
>
>   Branch  Description
>   --
>   json-code-v21   Source Code only
>   json-code+data-v21  Both code and data(for build/test/pull)
> 

Sukadev

Re: [bug] crypto/vmx/p8_ghash memory corruption in 4.8-rc7

[Marcelo Cerri]

Jan, 

Can you check if the problem occurs with this patch?

---
 drivers/crypto/vmx/ghash.c | 28 +---
 drivers/crypto/vmx/vmx.c   |  9 +
 2 files changed, 26 insertions(+), 11 deletions(-)

diff --git a/drivers/crypto/vmx/ghash.c b/drivers/crypto/vmx/ghash.c
index 6c999cb0..033aba1 100644
--- a/drivers/crypto/vmx/ghash.c
+++ b/drivers/crypto/vmx/ghash.c
@@ -36,6 +36,8 @@
 #define GHASH_DIGEST_SIZE (16)
 #define GHASH_KEY_LEN (16)
 
+#define GHASH_FALLBACK_ALG "ghash-generic"
+
 void gcm_init_p8(u128 htable[16], const u64 Xi[2]);
 void gcm_gmult_p8(u64 Xi[2], const u128 htable[16]);
 void gcm_ghash_p8(u64 Xi[2], const u128 htable[16],
@@ -53,18 +55,26 @@ struct p8_ghash_desc_ctx {
struct shash_desc fallback_desc;
 };
 
+int p8_ghash_fallback_descsize(void)
+{
+   int descsize;
+   struct crypto_shash *fallback;
+   fallback = crypto_alloc_shash(GHASH_FALLBACK_ALG, 0,
+ CRYPTO_ALG_NEED_FALLBACK);
+   if (IS_ERR(fallback)) {
+   return PTR_ERR(fallback);
+   }
+   descsize = crypto_shash_descsize(fallback);
+   crypto_free_shash(fallback);
+   return descsize;
+}
+
 static int p8_ghash_init_tfm(struct crypto_tfm *tfm)
 {
-   const char *alg;
+   const char *alg = GHASH_FALLBACK_ALG;
struct crypto_shash *fallback;
-   struct crypto_shash *shash_tfm = __crypto_shash_cast(tfm);
struct p8_ghash_ctx *ctx = crypto_tfm_ctx(tfm);
 
-   if (!(alg = crypto_tfm_alg_name(tfm))) {
-   printk(KERN_ERR "Failed to get algorithm name.\n");
-   return -ENOENT;
-   }
-
fallback = crypto_alloc_shash(alg, 0, CRYPTO_ALG_NEED_FALLBACK);
if (IS_ERR(fallback)) {
printk(KERN_ERR
@@ -79,10 +89,6 @@ static int p8_ghash_init_tfm(struct crypto_tfm *tfm)
   crypto_shash_get_flags((struct crypto_shash
   *) tfm));
ctx->fallback = fallback;
-
-   shash_tfm->descsize = sizeof(struct p8_ghash_desc_ctx)
-   + crypto_shash_descsize(fallback);
-
return 0;
 }
 
diff --git a/drivers/crypto/vmx/vmx.c b/drivers/crypto/vmx/vmx.c
index 31a98dc..8a51149 100644
--- a/drivers/crypto/vmx/vmx.c
+++ b/drivers/crypto/vmx/vmx.c
@@ -28,6 +28,8 @@
 #include 
 #include 
 
+int p8_ghash_fallback_descsize(void);
+
 extern struct shash_alg p8_ghash_alg;
 extern struct crypto_alg p8_aes_alg;
 extern struct crypto_alg p8_aes_cbc_alg;
@@ -45,6 +47,7 @@ int __init p8_init(void)
 {
int ret = 0;
struct crypto_alg **alg_it;
+   int ghash_descsize;
 
for (alg_it = algs; *alg_it; alg_it++) {
ret = crypto_register_alg(*alg_it);
@@ -59,6 +62,12 @@ int __init p8_init(void)
if (ret)
return ret;
 
+   ghash_descsize = p8_ghash_fallback_descsize();
+   if (ghash_descsize < 0) {
+   printk(KERN_ERR "Cannot get descsize for p8_ghash fallback\n");
+   return ghash_descsize;
+   }
+   p8_ghash_alg.descsize += ghash_descsize;
ret = crypto_register_shash(_ghash_alg);
if (ret) {
for (alg_it = algs; *alg_it; alg_it++)
-- 
2.7.4



signature.asc
Description: PGP signature

Re: [bug] crypto/vmx/p8_ghash memory corruption in 4.8-rc7

[Jan Stancek]

- Original Message -
> From: "Herbert Xu" 
> To: "Marcelo Cerri" 
> Cc: "Jan Stancek" , "rui y wang" , 
> mhce...@linux.vnet.ibm.com,
> leosi...@linux.vnet.ibm.com, pfsmor...@linux.vnet.ibm.com, 
> linux-cry...@vger.kernel.org,
> linuxppc-dev@lists.ozlabs.org, linux-ker...@vger.kernel.org
> Sent: Tuesday, 27 September, 2016 5:08:26 AM
> Subject: Re: [bug] crypto/vmx/p8_ghash memory corruption in 4.8-rc7
> 
> On Mon, Sep 26, 2016 at 02:43:17PM -0300, Marcelo Cerri wrote:
> > 
> > Wouldn't be enough to provide a pair of import/export functions as the
> > padlock-sha driver does?
> 
> I don't think that will help as ultimately you need to call the
> export function on the fallback and that's what requires the extra
> memory.  In fact very operation involving the fallback will need
> that extra memory too.

So, if we extended p8_ghash_desc_ctx to accommodate fallback_desc's ctx
and then provided statesize/import/export, would that be acceptable?

struct p8_ghash_desc_ctx {
...
struct shash_desc fallback_desc;
+   char fallback_ctx[sizeof(struct ghash_desc_ctx)];


Also, does that mean that padlock_sha has similar problem?
It does not seem to reserve any space for fallback __ctx and it calls
init()/update()/export() with padlock_sha_desc's fallback:

struct padlock_sha_desc {
struct shash_desc fallback;
};

static struct shash_alg sha1_alg = {
.descsize   =   sizeof(struct padlock_sha_desc),

Regards,
Jan

> 
> Cheers,
> --
> Email: Herbert Xu 
> Home Page: http://gondor.apana.org.au/~herbert/
> PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
> 

Re: [PATCH 2/2] bpf samples: update tracex5 sample to use __seccomp_filter

[David Miller]

From: "Naveen N. Rao" 
Date: Sat, 24 Sep 2016 02:10:05 +0530

> seccomp_phase1() does not exist anymore. Instead, update sample to use
> __seccomp_filter(). While at it, set max locked memory to unlimited.
> 
> Signed-off-by: Naveen N. Rao 

Also applied to net-next, thanks.

Re: [PATCH 1/2] bpf samples: fix compiler errors with sockex2 and sockex3

[David Miller]

From: "Naveen N. Rao" 
Date: Sat, 24 Sep 2016 02:10:04 +0530

> These samples fail to compile as 'struct flow_keys' conflicts with
> definition in net/flow_dissector.h. Fix the same by renaming the
> structure used in the sample.
> 
> Signed-off-by: Naveen N. Rao 

Applied to net-next.

Re: [PATCH] powerpc: Align hot loops of memset() and backwards_memcpy()

[Nicholas Piggin]

On Sun, 25 Sep 2016 21:36:59 +1000
Anton Blanchard  wrote:

> Hi Nick,
> 
> > Hmm. If we execute this loop once, we'll only fetch additional nops.
> > Twice, and we make up for them by not fetching unused instructions.
> > More than twice and we may start winning.
> > 
> > For large sizes it probably helps, but I'd like to see what sizes
> > memset sees.  
> 
> I noticed this in an nginx web serving test. There are some 1 and 2
> iteration calls, but quite a few larger ones - get_empty_filp() goes for
> 4 iterations and sk_prot_alloc() for 26 iterations.

Hi Anton,

I didn't have anything against the patch as such, I just wondered if
it's likely to be an overall win.

Thanks,
Nick