[GIT PULL 00/20] perf/core improvements and fixes

/core (2016-12-02 10:08:03 +0100) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo-20161205 for you to fetch changes up to bec60e50af83741cde1786ab475d4bf472aed6f9: perf annotate: Show raw form for jump

Re: [PATCH v8 1/3] perf annotate: Show raw form for jump instruction with indirect target

Em Mon, Dec 05, 2016 at 05:21:42PM -0300, Arnaldo Carvalho de Melo escreveu: > Em Mon, Dec 05, 2016 at 09:26:45PM +0530, Ravi Bangoria escreveu: > > For jump instructions that does not include target address as direct > > operand, show the original disassembled line for them. This is needed > >

Re: [PATCH v8 1/3] perf annotate: Show raw form for jump instruction with indirect target

Em Mon, Dec 05, 2016 at 09:26:45PM +0530, Ravi Bangoria escreveu: > For jump instructions that does not include target address as direct > operand, show the original disassembled line for them. This is needed > for certain powerpc jump instructions that use target address in a > register (such as

[PATCH 20/20] perf annotate: Show raw form for jump instruction with indirect target

From: Ravi Bangoria For jump instructions that does not include target address as direct operand, show the original disassembled line for them. This is needed for certain powerpc jump instructions that use target address in a register (such as bctr, btar, ...).

Re: [PATCH] PPC: sstep.c: Add modsw, moduw instruction emulation

Hi Naveen, Thanks for the review. >> --- >> arch/powerpc/lib/sstep.c | 9 + >> 1 file changed, 9 insertions(+) >> >> diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c >> index 9c78a9c..5acef72 100644 >> --- a/arch/powerpc/lib/sstep.c >> +++ b/arch/powerpc/lib/sstep.c >>

Re: [PATCH v2] of/irq: improve error report on irq discovery process failure

On 12/05/2016 12:28 PM, Rob Herring wrote: > On Mon, Dec 5, 2016 at 7:59 AM, Guilherme G. Piccoli > wrote: >> On PowerPC machines some PCI slots might not have level triggered >> interrupts capability (also know as level signaled interrupts), >> leading

Re: [PATCH v8 1/3] perf annotate: Show raw form for jump instruction with indirect target

Em Mon, Dec 05, 2016 at 09:26:45PM +0530, Ravi Bangoria escreveu: > For jump instructions that does not include target address as direct > operand, show the original disassembled line for them. This is needed > for certain powerpc jump instructions that use target address in a > register (such as

Re: [PATCH v8 1/6] powerpc/qspinlock: powerpc support qspinlock

On Mon, Dec 05, 2016 at 10:19:21AM -0500, Pan Xinhui wrote: > This patch add basic code to enable qspinlock on powerpc. qspinlock is > one kind of fairlock implementation. And seen some performance improvement > under some scenarios. > > queued_spin_unlock() release the lock by just one write of

Re: [PATCH v8 3/6] powerpc: lib/locks.c: Add cpu yield/wake helper function

On Mon, Dec 05, 2016 at 10:19:23AM -0500, Pan Xinhui wrote: > Add two corresponding helper functions to support pv-qspinlock. > > For normal use, __spin_yield_cpu will confer current vcpu slices to the > target vcpu(say, a lock holder). If target vcpu is not specified or it > is in running state,

Re: [PATCH v3 2/3] powerpc: get hugetlbpage handling more generic

On Wed, 2016-09-21 at 10:11 +0200, Christophe Leroy wrote: > Today there are two implementations of hugetlbpages which are managed > by exclusive #ifdefs: > * FSL_BOOKE: several directory entries points to the same single hugepage > * BOOK3S: one upper level directory entry points to a table of

Re: [PATCH v8 2/6] powerpc: pSeries/Kconfig: Add qspinlock build config

在 2016/12/6 08:58, Boqun Feng 写道: On Mon, Dec 05, 2016 at 10:19:22AM -0500, Pan Xinhui wrote: pSeries/powerNV will use qspinlock from now on. Signed-off-by: Pan Xinhui --- arch/powerpc/platforms/pseries/Kconfig | 8 1 file changed, 8 insertions(+)

[PATCH] powerpc/64s: tidy up after exception handler rework

Somewhere along the line, search/replace left some naming garbled, and untidy alignment. Might as well fix them all up now while git blame history doesn't extend too far. Signed-off-by: Nicholas Piggin --- arch/powerpc/include/asm/head-64.h | 160

Re: [PATCH v8 1/6] powerpc/qspinlock: powerpc support qspinlock

correct waiman's address. 在 2016/12/6 08:47, Boqun Feng 写道: On Mon, Dec 05, 2016 at 10:19:21AM -0500, Pan Xinhui wrote: This patch add basic code to enable qspinlock on powerpc. qspinlock is one kind of fairlock implementation. And seen some performance improvement under some scenarios.

[PATCH RFC v2 3/3] powerpc/64: Enable use of radix MMU under hypervisor on POWER9

To use radix as a guest, we first need to tell the hypervisor via the ibm,client-architecture call first that we support POWER9 and architecture v3.00, and that we can do either radix or hash and that we would like to choose later using an hcall (the H_REGISTER_PROC_TBL hcall). Then we need to

Re: [PATCH v8 2/6] powerpc: pSeries/Kconfig: Add qspinlock build config

On Mon, Dec 05, 2016 at 10:19:22AM -0500, Pan Xinhui wrote: > pSeries/powerNV will use qspinlock from now on. > > Signed-off-by: Pan Xinhui > --- > arch/powerpc/platforms/pseries/Kconfig | 8 > 1 file changed, 8 insertions(+) > > diff --git

Re: [PATCH v8 3/6] powerpc: lib/locks.c: Add cpu yield/wake helper function

在 2016/12/6 09:23, Boqun Feng 写道: On Mon, Dec 05, 2016 at 10:19:23AM -0500, Pan Xinhui wrote: Add two corresponding helper functions to support pv-qspinlock. For normal use, __spin_yield_cpu will confer current vcpu slices to the target vcpu(say, a lock holder). If target vcpu is not

[RFC][PATCH] powerpc/64s: use start, size rather than start, end for exception handlers

start,size has the benefit of being easier to search for (start,end usually gives you the preceeding vector from the one you want, as first result). Suggested-by: Benjamin Herrenschmidt Signed-off-by: Nicholas Piggin ---

Re: [PATCH v8 2/6] powerpc: pSeries/Kconfig: Add qspinlock build config

在 2016/12/6 09:24, Pan Xinhui 写道: 在 2016/12/6 08:58, Boqun Feng 写道: On Mon, Dec 05, 2016 at 10:19:22AM -0500, Pan Xinhui wrote: pSeries/powerNV will use qspinlock from now on. Signed-off-by: Pan Xinhui --- arch/powerpc/platforms/pseries/Kconfig | 8

Re: [PATCH 1/1] serial/uuc_uart: Set shutdown timeout to CONFIG_HZ independent 2ms

On Monday 05 December 2016 10:04:27, Timur Tabi wrote: > Alexander Stein wrote: > > - schedule_timeout(2); > > + schedule_timeout(msecs_to_jiffies(2)); > > NACK. > > So I don't remember why I wrote this code, but I don't think I was > expecting it to be 2ms. Instead, I think

[PATCH 2/3] powerpc: correctly disable latent entropy GCC plugin on prom_init.o

Commit 38addce8b600 ("gcc-plugins: Add latent_entropy plugin") excludes certain powerpc early boot code from the latent entropy plugin by adding appropriate CFLAGS. It looks like this was supposed to cover prom_init.o, but ended up saying init.o (which doesn't exist) instead. Fix the typo. Fixes:

[PATCH 3/3] powerpc: enable support for GCC plugins

Enable support for GCC plugins on powerpc. Add an additional version check in gcc-plugins-check to advise users to upgrade to gcc 5.2+ on powerpc to avoid issues with header files (gcc <= 4.6) or missing copies of rs6000-cpus.def (4.8 to 5.1 on 64-bit targets). Signed-off-by: Andrew Donnellan

Re: [PATCH] PPC: sstep.c: Add modsw, moduw instruction emulation

By the way, I missed mentioning previously: please use 'powerpc: ' prefix for the subject, rather than PPC. On 2016/12/04 10:25PM, PrasannaKumar Muralidharan wrote: > Add modsw and moduw instruction emulation support to analyse_instr. And, it will be better if you can briefly describe what

Re: [PATCH] cxl: prevent read/write to AFU config space while AFU not configured

Acked-by: Ian Munsie Looks like a reasonable solution > Pradipta found this while doing testing for cxlflash. I've tested this > patch and I'm satisfied that it solves the issue, but I've asked Pradipta > to test it a bit further. :)

Re: [PATCH 1/3] KVM: PPC: Book3S: Change interrupt call to reduce scratch space use on HV

On Thu, Dec 01, 2016 at 06:18:10PM +1100, Nicholas Piggin wrote: > Change the calling convention to put the trap number together with > CR in two halves of r12, which frees up HSTATE_SCRATCH2 in the HV > handler, and r9 free. Cute idea! Some comments below... > The 64-bit PR handler entry

Re: [PATCH] PPC: sstep.c: Add modsw, moduw instruction emulation

On 2016/12/06 01:21AM, PrasannaKumar Muralidharan wrote: > >> + > >> + case 267: /* moduw */ > > > > Please move this case further up so that the extended opcodes are in > > numerical order. > > Placed it after divide instruction as it appeared logical. Also placed > 267 below

Re: [PATCH v3 2/3] powerpc: get hugetlbpage handling more generic

Le 06/12/2016 à 02:18, Scott Wood a écrit : On Wed, 2016-09-21 at 10:11 +0200, Christophe Leroy wrote: Today there are two implementations of hugetlbpages which are managed by exclusive #ifdefs: * FSL_BOOKE: several directory entries points to the same single hugepage * BOOK3S: one upper

Re: [PATCH 1/2] powerpc/powernv/opal-dump : Handles opal_dump_info properly

Hi Michael, Can you please have a look at this patchset as there is no functional changes involve with this? Thanks, Mukesh On Thursday 01 December 2016 02:38 PM, Mukesh Ojha wrote: Moves the return value check of 'opal_dump_info' to a proper place which was previously unnecessarily

Re: [PATCH v8 2/3] perf annotate: Support jump instruction with target as second operand

Hi Arnaldo, Hmm, so it's difficult to find example of this when we use debuginfo. Because... Jump__parse tries to look for two things 'offset' and 'target address'. objdump with debuginfo will include offset in assembly f.e. annotate of 'smp_call_function_single' with perf.data and vmlinux I

[PATCH 1/3] gcc-plugins: fix definition of DISABLE_LATENT_ENTROPY_PLUGIN

The variable DISABLE_LATENT_ENTROPY_PLUGIN is defined when CONFIG_PAX_LATENT_ENTROPY is set. This is leftover from the original PaX version of the plugin code and doesn't actually exist. Change the condition to depend on CONFIG_GCC_PLUGIN_LATENT_ENTROPY instead. Fixes: 38addce8b600 ("gcc-plugins:

[GIT PULL] Please pull powerpc/linux.git powerpc-4.9-7 tag

Hi Linus, Please pull what is hopefully the last batch of powerpc fixes for 4.9. The following changes since commit 984d7a1ec67ce3a46324fa4bcb4c745bbc266cf2: powerpc/mm: Fixup kernel read only mapping (2016-11-25 14:18:25 +1100) are available in the git repository at:

[PATCH v8 1/6] powerpc/qspinlock: powerpc support qspinlock

This patch add basic code to enable qspinlock on powerpc. qspinlock is one kind of fairlock implementation. And seen some performance improvement under some scenarios. queued_spin_unlock() release the lock by just one write of NULL to the ::locked field which sits at different places in the two

[PATCH v8 6/6] powerpc/pv-qspinlock: Optimise native unlock path

Avoid a function call under native version of qspinlock. On powerNV, bafore applying this patch, every unlock is expensive. This small optimizes enhance the performance. We use static_key with jump_label which removes unnecessary loads of lppaca and its stuff. Signed-off-by: Pan Xinhui

[PATCH v8 5/6] powerpc: pSeries: Add pv-qspinlock build config/make

pSeries run as a guest and might need pv-qspinlock. Signed-off-by: Pan Xinhui --- arch/powerpc/kernel/Makefile | 1 + arch/powerpc/platforms/pseries/Kconfig | 8 2 files changed, 9 insertions(+) diff --git a/arch/powerpc/kernel/Makefile

[PATCH v8 3/6] powerpc: lib/locks.c: Add cpu yield/wake helper function

Add two corresponding helper functions to support pv-qspinlock. For normal use, __spin_yield_cpu will confer current vcpu slices to the target vcpu(say, a lock holder). If target vcpu is not specified or it is in running state, such conferging to lpar happens or not depends. Because hcall itself

[PATCH v8 2/6] powerpc: pSeries/Kconfig: Add qspinlock build config

pSeries/powerNV will use qspinlock from now on. Signed-off-by: Pan Xinhui --- arch/powerpc/platforms/pseries/Kconfig | 8 1 file changed, 8 insertions(+) diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig index

[PATCH v8 4/6] powerpc/pv-qspinlock: powerpc support pv-qspinlock

The default pv-qspinlock uses qspinlock(native version of pv-qspinlock). pv_lock initialization should be done in bootstage with irq disabled. And if we run as a guest with powerKVM/pHyp shared_processor mode, restore pv_lock_ops callbacks to pv-qspinlock(pv version) which makes full use of

[PATCH v8 0/6] Implement qspinlock/pv-qspinlock on ppc

Hi All, this is the fairlock patchset. You can apply them and build successfully. patches are based on linux-next qspinlock can avoid waiter starved issue. It has about the same speed in single-thread and it can be much faster in high contention situations especially when the spinlock is

Re: [RFC PATCH] PCI: designware: add host_init() error handling

Às 11:51 AM de 12/2/2016, Srinivas Kandagatla escreveu: > > > On 02/12/16 10:32, Joao Pinto wrote: >> >> Hi Srinivas, >> >> Às 11:51 AM de 12/1/2016, Srinivas Kandagatla escreveu: >>> drivers/pci/host/pci-dra7xx.c | 4 +++- >>> drivers/pci/host/pci-exynos.c | 4 +++- >>>

[PATCH] cxl: prevent read/write to AFU config space while AFU not configured

During EEH recovery, we deconfigure all AFUs whilst leaving the corresponding vPHB and virtual PCI device in place. If something attempts to interact with the AFU's PCI config space (e.g. running lspci) after the AFU has been deconfigured and before it's reconfigured,

[PATCH 1/3] powerpc/64: Fixes for the ibm,client-architecture-support options

This fixes the values for some of the option vector 5 bits in the ibm,client-architecture-support vector 5. The "platform facilities options" bits are in byte 17 not byte 14, so the upper 8 bits of their definitions need to be 0x11 not 0x0E. The "sub processor support" option is in byte 21 not

Re: [PATCH] PPC: sstep.c: Add modsw, moduw instruction emulation

On 2016/12/04 10:25PM, PrasannaKumar Muralidharan wrote: > Add modsw and moduw instruction emulation support to analyse_instr. > > Signed-off-by: PrasannaKumar Muralidharan Hi Prasanna, Thanks for the patch! A few minor comments below... > --- >

Re: [PATCH RFC 3/3] powerpc/64: Enable use of radix MMU under hypervisor on POWER9

On Mon, Dec 05, 2016 at 07:55:32PM +1100, Benjamin Herrenschmidt wrote: > On Mon, 2016-12-05 at 19:04 +1100, Paul Mackerras wrote: > > +   vec5 = of_get_flat_dt_prop(chosen, "ibm,architecture-vec-5", ); > > +   if (!vec5 || size <= OV5_INDX(OV5_MMU_RADIX_300)) > > +   return; >

[PATCH RFC 3/3] powerpc/64: Enable use of radix MMU under hypervisor on POWER9

To use radix as a guest, we first need to tell the hypervisor via the ibm,client-architecture call first that we support POWER9 and architecture v3.00, and that we can do either radix or hash and that we would like to choose later using an hcall (the H_REGISTER_PROC_TBL hcall). Then we need to

[PATCH RFC 2/3] powerpc/64: Always enable radix support for 64-bit Book 3S kernels

This removes the ability for the user to choose whether or not to include support for the radix MMU in kernels built to run on 64-bit Book 3S machines. Excluding radix support saves only about 25kiB of text and 13kiB of data, a total of little over half a page. Having the option expands the space

Re: [PATCH RFC 3/3] powerpc/64: Enable use of radix MMU under hypervisor on POWER9

On Mon, 2016-12-05 at 19:04 +1100, Paul Mackerras wrote: > +   vec5 = of_get_flat_dt_prop(chosen, "ibm,architecture-vec-5", ); > +   if (!vec5 || size <= OV5_INDX(OV5_MMU_RADIX_300)) > +   return; Could be bike shedding but shouldn't we first check if we are in an LPAR and

Re: [RFC][PATCH] powerpc/oops: Provide disassembly on OOPS

Balbir Singh writes: > This patch is tied to xmon, it can be refactored out > better later if required. The idea is to provide > disassembly using xmon so that when we get an OOPS > we see something like the following below > > ... > NIP [c063a230]

[PATCH v2] of/irq: improve error report on irq discovery process failure

On PowerPC machines some PCI slots might not have level triggered interrupts capability (also know as level signaled interrupts), leading of_irq_parse_pci() to complain by presenting error messages on the kernel log - in this case, the properties "interrupt-map" and "interrupt-map-mask" are not

Re: [PATCH v2] of/irq: improve error report on irq discovery process failure

On Mon, Dec 5, 2016 at 7:59 AM, Guilherme G. Piccoli wrote: > On PowerPC machines some PCI slots might not have level triggered > interrupts capability (also know as level signaled interrupts), > leading of_irq_parse_pci() to complain by presenting error messages > on

[PATCH 1/1] serial/uuc_uart: Set shutdown timeout to CONFIG_HZ independent 2ms

schedule_timeout takes a timeout in jiffies resolution. So pass 2ms as a converted jiffies value. This makes the timeout independent of CONFIG_HZ. Signed-off-by: Alexander Stein --- drivers/tty/serial/ucc_uart.c | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH v8 2/3] perf annotate: Support jump instruction with target as second operand

Arch like powerpc has jump instructions that includes target address as second operand. For example, 'bne cr7,0xc00f6154'. Add support for such instruction in perf annotate. objdump o/p: c00f6140: ld r9,1032(r31) c00f6144: cmpdi cr7,r9,0 c00f6148:

[PATCH v8 3/3] perf annotate: Fix jump target outside of function address range

If jump target is outside of function range, perf is not handling it correctly. Especially when target address is lesser than function start address, target offset will be negative. But, target address declared to be unsigned, converts negative number into 2's complement. See below example. Here

[PATCH v8 1/3] perf annotate: Show raw form for jump instruction with indirect target

For jump instructions that does not include target address as direct operand, show the original disassembled line for them. This is needed for certain powerpc jump instructions that use target address in a register (such as bctr, btar, ...). Before: ld r12,32088(r12) mtctr r12 v

Re: [PATCH 1/1] serial/uuc_uart: Set shutdown timeout to CONFIG_HZ independent 2ms

Alexander Stein wrote: - schedule_timeout(2); + schedule_timeout(msecs_to_jiffies(2)); NACK. So I don't remember why I wrote this code, but I don't think I was expecting it to be 2ms. Instead, I think I just wanted it to be some delay, but I believed that