[PATCH] powerpc/mm: Update mm context addr limit correctly.

We added the addr < TASK_SIZE check to avoid updating addr_limit unnecessarily and also to avoid calling slice_flush_segments on all the cpus. This had the side effect of having different behaviour when using an addr value above TASK_SIZE before updating addr_limit and after updating addr_limit

[PATCH v4 4/5] perf report: Show branch type statistics for stdio mode

Show the branch type statistics at the end of perf report --stdio. For example: perf report --stdio JCC forward: 27.8% JCC backward: 9.7% CROSS_4K: 0.0% CROSS_2M: 14.3% JCC: 37.6% JMP: 0.0% IND_JMP: 6.5% CALL: 26.6% RET: 29.3%

[PATCH v4 0/5] perf report: Show branch type

v4: --- 1. Describe the major changes in patch description. Thanks for Peter Zijlstra's reminding. 2. Initialize branch type to 0 in intel_pmu_lbr_read_32 and intel_pmu_lbr_read_64. Remove the invalid else code in intel_pmu_lbr_filter. v3: --- 1. Move the JCC forward/backward and

[PATCH v4 3/5] perf record: Create a new option save_type in --branch-filter

The option indicates the kernel to save branch type during sampling. One example: perf record -g --branch-filter any,save_type Signed-off-by: Jin Yao --- tools/perf/Documentation/perf-record.txt | 1 + tools/perf/util/parse-branch-options.c | 1 + 2 files changed, 2

[PATCH v4 2/5] perf/x86/intel: Record branch type

Perf already has support for disassembling the branch instruction and using the branch type for filtering. The patch just records the branch type in perf_branch_entry. Before recording, the patch converts the x86 branch type to common branch type. Comparing to previous version, the major changes

[PATCH v4 1/5] perf/core: Define the common branch type classification

It is often useful to know the branch types while analyzing branch data. For example, a call is very different from a conditional branch. Currently we have to look it up in binary while the binary may later not be available and even the binary is available but user has to take some time. It is

[PATCH v4 5/5] perf report: Show branch type in callchain entry

Show branch type in callchain entry. The branch type is printed with other LBR information (such as cycles/abort/...). One example: perf report --branch-history --stdio --no-children --23.54%--main div.c:42 (CROSS_2M RET cycles:2) compute_flag div.c:28 (RET cycles:2)

Re: [PATCH V4 7/7] cxl: Add psl9 specific code

Le 07/04/2017 à 16:11, Christophe Lombard a écrit : The new Coherent Accelerator Interface Architecture, level 2, for the IBM POWER9 brings new content and features: - POWER9 Service Layer - Registers - Radix mode - Process element entry - Dedicated-Shared Process Programming Model -

[PATCH 2/9] mm/huge_memory: Deposit a pgtable for DAX PMD faults when required

Although all architectures use a deposited page table for THP on anonymous VMAs some architectures (s390 and powerpc) require the deposited storage even for file backed VMAs due to quirks of their MMUs. This patch adds support for depositing a table in DAX PMD fault handling path for archs that

Re: WARN @lib/refcount.c:128 during hot unplug of I/O adapter.

On 04/11/2017 02:00 AM, Michael Ellerman wrote: > Tyrel Datwyler writes: > >> On 04/06/2017 09:04 PM, Michael Ellerman wrote: >>> Tyrel Datwyler writes: >>> On 04/06/2017 03:27 AM, Sachin Sant wrote: > On a POWER8 LPAR running

[PATCH 1/9] mm/huge_memory: Use zap_deposited_table() more

Depending flags of the PMD being zapped there may or may not be a deposited pgtable to be freed. In two of the three cases this is open coded while the third uses the zap_deposited_table() helper. This patch converts the others to use the helper to clean things up a bit. Cc: "Aneesh Kumar K.V"

[PATCH 3/9] powerpc/mm: Add _PAGE_DEVMAP for ppc64.

From: "Aneesh Kumar K.V" Add a _PAGE_DEVMAP bit for PTE and DAX PMD entires. PowerPC doesn't currently support PUD faults so we haven't extended it to the PUD level. Cc: Aneesh Kumar K.V Signed-off-by: Oliver O'Halloran

[PATCH 5/9] powerpc/vmemmap: Add altmap support

Adds support to powerpc for the altmap feature of ZONE_DEVICE memory. An altmap is a driver provided region that is used to provide the backing storage for the struct pages of ZONE_DEVICE memory. In situations where large amount of ZONE_DEVICE memory is being added to the system the altmap reduces

[PATCH 6/9] powerpc, mm: Enable ZONE_DEVICE on powerpc

Flip the switch. Running around and screaming "IT'S ALIVE" is optional, but recommended. Signed-off-by: Oliver O'Halloran --- mm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mm/Kconfig b/mm/Kconfig index 43d000e44424..d696af58f97f 100644 ---

[PATCH 9/9] powerpc: Add pmem API support

Initial powerpc support for the arch-specific bit of the persistent memory API. Nothing fancy here. Signed-off-by: Oliver O'Halloran --- arch/powerpc/Kconfig| 1 + arch/powerpc/include/asm/pmem.h | 109

ZONE_DEVICE and pmem API support for powerpc

could sanity check this series I'd appreciate it. Series is based on next-20170411, but it should apply elsewhere with minor fixups to arch_{add|remove}_memory due to conflicts with HMM. For those interested in testing this, there is a driver and matching firmware that carves out some system memory

[PATCH 4/9] powerpc/mm: Reshuffle vmemmap_free()

Removes an indentation level and shuffles some code around to make the following patch cleaner. No functional changes. Signed-off-by: Oliver O'Halloran --- arch/powerpc/mm/init_64.c | 47 +-- 1 file changed, 25 insertions(+), 22

[PATCH 7/9] powerpc/mm: Wire up ioremap_cache

The default implementation of ioremap_cache() is aliased to ioremap(). On powerpc ioremap() creates cache-inhibited mappings by default which is almost certainly not what you wanted. Signed-off-by: Oliver O'Halloran --- arch/powerpc/include/asm/io.h | 2 ++ 1 file changed, 2

[PATCH 8/9] powerpc/mm: Wire up hpte_removebolted for powernv

From: Rashmica Gupta Adds support for removing bolted (i.e kernel linear mapping) mappings on powernv. This is needed to support memory hot unplug operations which are required for the teardown of DAX/PMEM devices. Cc: Rashmica Gupta Cc: Anton

Re: ZONE_DEVICE and pmem API support for powerpc

kml/2017/3/19/146 > Series is based on next-20170411, but it should apply elsewhere with minor > fixups to arch_{add|remove}_memory due to conflicts with HMM. For those > interested in testing this, there is a driver and matching firmware that > carves > out some system memory for u

Re: [PATCH 8/9] powerpc/mm: Wire up hpte_removebolted for powernv

Hi Oliver, > From: Rashmica Gupta > > Adds support for removing bolted (i.e kernel linear mapping) mappings > on powernv. This is needed to support memory hot unplug operations > which are required for the teardown of DAX/PMEM devices. > > Cc: Rashmica Gupta

Re: [PATCH 4/9] powerpc/mm: Reshuffle vmemmap_free()

Hi Oliver, On Wed, 12 Apr 2017 03:42:28 +1000 Oliver O'Halloran wrote: > > diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c > index ec84b31c6c86..f8124edb6ffa 100644 > --- a/arch/powerpc/mm/init_64.c > +++ b/arch/powerpc/mm/init_64.c > @@ -234,12 +234,15 @@

Re: [PATCH 6/9] powerpc, mm: Enable ZONE_DEVICE on powerpc

Stephen Rothwell writes: > Hi Oliver, > > On Wed, 12 Apr 2017 03:42:30 +1000 Oliver O'Halloran wrote: >> >> Flip the switch. Running around and screaming "IT'S ALIVE" is optional, >> but recommended. >> >> Signed-off-by: Oliver O'Halloran

[PATCH 1/2] lib/raid6: Build proper files on corresponding arch

Previously the raid6 test Makefile did not correctly build the files for testing on PowerPC. This patch fixes the bug, so that all appropriate files for PowerPC are built. Signed-off-by: Matt Brown --- lib/raid6/test/Makefile | 8 +--- 1 file changed, 5

Re: [PATCH 8/9] powerpc/mm: Wire up hpte_removebolted for powernv

On Wed, 2017-04-12 at 03:42 +1000, Oliver O'Halloran wrote: > From: Rashmica Gupta > > Adds support for removing bolted (i.e kernel linear mapping) mappings on > powernv. This is needed to support memory hot unplug operations which > are required for the teardown of

Re: [PATCH V4 6/7] cxl: Isolate few psl8 specific calls

Frederic Barrat writes: > Le 07/04/2017 à 16:11, Christophe Lombard a écrit : >> Point out the specific Coherent Accelerator Interface Architecture, >> level 1, registers. >> Code and functions specific to PSL8 (CAIA1) must be framed. >> >> Signed-off-by: Christophe

Re: [PATCH 6/9] powerpc, mm: Enable ZONE_DEVICE on powerpc

On Wed, 2017-04-12 at 03:42 +1000, Oliver O'Halloran wrote: > Flip the switch. Running around and screaming "IT'S ALIVE" is optional, > but recommended. > > Signed-off-by: Oliver O'Halloran > --- > mm/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff

Re: [PATCH 6/9] powerpc, mm: Enable ZONE_DEVICE on powerpc

Hi Oliver, On Wed, 12 Apr 2017 03:42:30 +1000 Oliver O'Halloran wrote: > > Flip the switch. Running around and screaming "IT'S ALIVE" is optional, > but recommended. > > Signed-off-by: Oliver O'Halloran > --- > mm/Kconfig | 2 +- > 1 file changed, 1

Re: [PATCH 3/9] powerpc/mm: Add _PAGE_DEVMAP for ppc64.

On Wednesday 12 April 2017 05:49 AM, Stephen Rothwell wrote: Hi Oliver, On Wed, 12 Apr 2017 03:42:27 +1000 Oliver O'Halloran wrote: From: "Aneesh Kumar K.V" Add a _PAGE_DEVMAP bit for PTE and DAX PMD entires. PowerPC doesn't currently

Re: [PATCH 8/9] powerpc/mm: Wire up hpte_removebolted for powernv

On 12/04/17 10:18, Stephen Rothwell wrote: Hi Oliver, On Wed, 12 Apr 2017 08:50:56 +1000 Anton Blanchard wrote: From: Rashmica Gupta Adds support for removing bolted (i.e kernel linear mapping) mappings on powernv. This is needed to support memory

Re: [PATCH 5/9] powerpc/vmemmap: Add altmap support

On Wed, 2017-04-12 at 03:42 +1000, Oliver O'Halloran wrote: > Adds support to powerpc for the altmap feature of ZONE_DEVICE memory. An > altmap is a driver provided region that is used to provide the backing > storage for the struct pages of ZONE_DEVICE memory. In situations where > large amount

[PATCH v3 2/2] raid6/altivec: Add vpermxor implementation for raid6 Q syndrome

The raid6 Q syndrome check has been optimised using the vpermxor instruction. This instruction was made available with POWER8, ISA version 2.07. It allows for both vperm and vxor instructions to be done in a single instruction. This has been tested for correctness on a ppc64le vm with a basic

Re: EEH error in doing DMA with PEX 8619

On Tue, Apr 11, 2017 at 5:37 PM, Benjamin Herrenschmidt [via linuxppc] wrote: > Another possibility would be if the requests from the PLX have a > different initiator ID on the bus than the device you are setting up > the DMA for. Is there a way to

Re: powerpc/crypto/crc32c-vpmsum: Fix missing preempt_disable()

On Thu, 2017-04-06 at 13:34:38 UTC, Michael Ellerman wrote: > In crc32c_vpmsum() we call enable_kernel_altivec() without first > disabling preemption, which is not allowed: > > WARNING: CPU: 9 PID: 2949 at ../arch/powerpc/kernel/process.c:277 > enable_kernel_altivec+0x100/0x120 > Modules

Re: [PATCH 3/9] powerpc/mm: Add _PAGE_DEVMAP for ppc64.

Hi Oliver, On Wed, 12 Apr 2017 03:42:27 +1000 Oliver O'Halloran wrote: > > From: "Aneesh Kumar K.V" > > Add a _PAGE_DEVMAP bit for PTE and DAX PMD entires. PowerPC doesn't > currently support PUD faults so we haven't extended it to the PUD >

Re: [PATCH V4 7/7] cxl: Add psl9 specific code

Frederic Barrat writes: > Le 07/04/2017 à 16:11, Christophe Lombard a écrit : >> The new Coherent Accelerator Interface Architecture, level 2, for the >> IBM POWER9 brings new content and features: >> - POWER9 Service Layer >> - Registers >> - Radix mode >> - Process

Re: [PATCH 8/9] powerpc/mm: Wire up hpte_removebolted for powernv

Hi Oliver, On Wed, 12 Apr 2017 08:50:56 +1000 Anton Blanchard wrote: > > > From: Rashmica Gupta > > > > Adds support for removing bolted (i.e kernel linear mapping) mappings > > on powernv. This is needed to support memory hot unplug operations > > which

Re: ZONE_DEVICE and pmem API support for powerpc

Hi Oliver, On Wed, 12 Apr 2017 03:42:24 +1000 Oliver O'Halloran <ooh...@gmail.com> wrote: > > Series is based on next-20170411, but it should apply elsewhere with minor > fixups to arch_{add|remove}_memory due to conflicts with HMM. For those Just to make life fun for you, And

[PATCH] powerpc/mm/hash: don't opencode VMALLOC_INDEX

Also remove wrong indentation to fix checkpatch.pl warning. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/mm/slb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c index

Re: EEH error in doing DMA with PEX 8619

On Tue, 2017-04-11 at 18:39 -0700, IanJiang wrote: > On Tue, Apr 11, 2017 at 5:37 PM, Benjamin Herrenschmidt [via > linuxppc] > wrote: > > > Another possibility would be if the requests from the PLX have a  > > different initiator ID on the bus than the

Re: WARN @lib/refcount.c:128 during hot unplug of I/O adapter.

Tyrel Datwyler writes: > On 04/11/2017 02:00 AM, Michael Ellerman wrote: >> Tyrel Datwyler writes: >>> I started looking at it when Bharata submitted a patch trying to fix the >>> issue for CPUs, but got side tracked by other things. I

Re: [RFC PATCH 6/7] powerpc/hugetlb: Add code to support to follow huge page directory entries

On 04/11/2017 03:55 PM, Michael Ellerman wrote: > "Aneesh Kumar K.V" writes: > >> Add follow_huge_pd implementation for ppc64. >> >> Signed-off-by: Aneesh Kumar K.V >> --- >> arch/powerpc/mm/hugetlbpage.c | 42 >>

Re: [PATCH 1/2] powerpc/mm: fix up pgtable dump flags

On 31/03/17 12:37, Oliver O'Halloran wrote: On Book3s we have two PTE flags used to mark cache-inhibited mappings: _PAGE_TOLERANT and _PAGE_NON_IDEMPOTENT. Currently the kernel page table dumper only looks at the generic _PAGE_NO_CACHE which is defined to be _PAGE_TOLERANT. This patch modifies

Re: [PATCH 2/9] mm/huge_memory: Deposit a pgtable for DAX PMD faults when required

Oliver O'Halloran writes: > Although all architectures use a deposited page table for THP on anonymous > VMAs > some architectures (s390 and powerpc) require the deposited storage even for > file backed VMAs due to quirks of their MMUs. This patch adds support for > depositing

Re: [PATCH 2/2] powerpc/mm: add phys addr to linux page table dump

On 31/03/17 12:37, Oliver O'Halloran wrote: The current page table dumper scans the linux page tables and coalesces mappings with adjacent virtual addresses and similar PTE flags. This behaviour is somewhat broken when you consider the IOREMAP space where entirely unrelated mappings will

Re: [PATCH 1/9] mm/huge_memory: Use zap_deposited_table() more

Oliver O'Halloran writes: > Depending flags of the PMD being zapped there may or may not be a > deposited pgtable to be freed. In two of the three cases this is open > coded while the third uses the zap_deposited_table() helper. This patch > converts the others to use the

Re: [PATCH v2] ppc64/kprobe: Fix oops when kprobed on 'stdu' instruction

On Tue, Apr 11, 2017 at 10:38:13AM +0530, Ravi Bangoria wrote: > If we set a kprobe on a 'stdu' instruction on powerpc64, we see a kernel > OOPS: > > [ 1275.165932] Bad kernel stack pointer cd93c840 at c0009868 > [ 1275.166378] Oops: Bad kernel stack pointer, sig: 6 [#1] > ... >

Re: [PATCH v3 2/5] perf/x86/intel: Record branch type

On Tue, Apr 11, 2017 at 06:56:30PM +0800, Jin Yao wrote: > Perf already has support for disassembling the branch instruction > and using the branch type for filtering. The patch just records > the branch type in perf_branch_entry. > > Before recording, the patch converts the x86 branch

Re: [PATCH 1/2] powerpc/tracing: Trace TLBIE(L)

On Tue, 2017-04-11 at 15:23 +1000, Balbir Singh wrote: > Just a quick patch to trace tlbie(l)'s. The idea being that it can be > enabled when we suspect corruption or when we need to see if we are doing > the right thing during flush. I think the format can be enhanced to > make it nicer (expand

[PATCH kernel v2] powerpc/iommu: Do not call PageTransHuge() on tail pages

The CMA pages migration code does not support compound pages at the moment so it performs few tests before proceeding to actual page migration. One of the tests - PageTransHuge() - has VM_BUG_ON_PAGE(PageTail()) as it is designed to be called on head pages only. Since we also test for

Re: [PATCH v3 2/5] perf/x86/intel: Record branch type

On 4/11/2017 3:52 PM, Peter Zijlstra wrote: This is still a completely inadequate changelog. I really will not accept patches like this. Hi, The changelog is added in the cover-letter ("[PATCH v3 0/5] perf report: Show branch type"). Does the changelog need to be added in each patch's

Re: kselftest:lost_exception_test failure with 4.11.0-rc5

Madhavan Srinivasan writes: > On Friday 07 April 2017 06:06 PM, Michael Ellerman wrote: >> Sachin Sant writes: >> >>> I have run into few instances where the lost_exception_test from >>> powerpc kselftest fails with SIGABRT. Following o/p is

Re: [PATCH v3 2/5] perf/x86/intel: Record branch type

On Tue, Apr 11, 2017 at 09:52:19AM +0200, Peter Zijlstra wrote: > On Tue, Apr 11, 2017 at 06:56:30PM +0800, Jin Yao wrote: > > @@ -960,6 +1006,11 @@ intel_pmu_lbr_filter(struct cpu_hw_events *cpuc) > > cpuc->lbr_entries[i].from = 0; > > compress = true; > >

Re: [PATCH kernel v2] powerpc/iommu: Do not call PageTransHuge() on tail pages

On Tue, 2017-04-11 at 17:54 +1000, Alexey Kardashevskiy wrote: > The CMA pages migration code does not support compound pages at > the moment so it performs few tests before proceeding to actual page > migration. > > One of the tests - PageTransHuge() - has VM_BUG_ON_PAGE(PageTail()) as > it is

Re: [PATCH kernel v2] powerpc/powernv: Check kzalloc() return value in pnv_pci_table_alloc

On 27/03/17 19:27, Alexey Kardashevskiy wrote: > pnv_pci_table_alloc() ignores possible failure from kzalloc_node(), > this adds a check. There are 2 callers of pnv_pci_table_alloc(), > one already checks for tbl!=NULL, this adds WARN_ON() to the other path > which only happens during boot time in

Re: [PATCH v2] ppc64/kprobe: Fix oops when kprobed on 'stdu' instruction

On Tue, 2017-04-11 at 10:38 +0530, Ravi Bangoria wrote: > If we set a kprobe on a 'stdu' instruction on powerpc64, we see a kernel > OOPS: > > [ 1275.165932] Bad kernel stack pointer cd93c840 at c0009868 > [ 1275.166378] Oops: Bad kernel stack pointer, sig: 6 [#1] > ... > GPR00:

Re: EEH error in doing DMA with PEX 8619

On Tue, 2017-04-11 at 02:26 -0700, IanJiang wrote: > I did another test: > - Call dma_set_mask_and_coherent(>dev, DMA_BIT_MASK(32)) in > probe; > - Use DMA address or BUS address in DMA > But EHH error remains. We need to dig out the details of the EEH error. It will tell us more precisely what

Re: [PATCH 1/5] powerpc/pseries: do not use msgsndp doorbells on POWER9 guests

Nicholas Piggin writes: > POWER9 hypervisors will not necessarily run guest threads together on > the same core at the same time, so msgsndp should not be used. I'm worried this is encoding the behaviour of a particular hypervisor in the guest kernel. If we *can't* use

Re: [PATCH 1/5] powerpc/pseries: do not use msgsndp doorbells on POWER9 guests

cc'ing Paul On Tue, 11 Apr 2017 20:10:17 +1000 Michael Ellerman wrote: > Nicholas Piggin writes: > > > POWER9 hypervisors will not necessarily run guest threads together on > > the same core at the same time, so msgsndp should not be used. > > I'm

Re: [PATCH v5 13/15] livepatch: change to a per-task consistency model

On Mon 2017-02-13 19:42:40, Josh Poimboeuf wrote: > Change livepatch to use a basic per-task consistency model. This is the > foundation which will eventually enable us to patch those ~10% of > security patches which change function or data semantics. This is the > biggest remaining piece needed

Re: [PATCH v3 2/5] perf/x86/intel: Record branch type

On 4/11/2017 4:35 PM, Peter Zijlstra wrote: On Tue, Apr 11, 2017 at 04:11:21PM +0800, Jin, Yao wrote: On 4/11/2017 3:52 PM, Peter Zijlstra wrote: This is still a completely inadequate changelog. I really will not accept patches like this. Hi, The changelog is added in the cover-letter

Re: [PATCH v3 2/5] perf/x86/intel: Record branch type

On 4/11/2017 4:18 PM, Peter Zijlstra wrote: On Tue, Apr 11, 2017 at 09:52:19AM +0200, Peter Zijlstra wrote: On Tue, Apr 11, 2017 at 06:56:30PM +0800, Jin Yao wrote: @@ -960,6 +1006,11 @@ intel_pmu_lbr_filter(struct cpu_hw_events *cpuc) cpuc->lbr_entries[i].from = 0;

Re: [RFC PATCH 6/7] powerpc/hugetlb: Add code to support to follow huge page directory entries

"Aneesh Kumar K.V" writes: > Add follow_huge_pd implementation for ppc64. > > Signed-off-by: Aneesh Kumar K.V > --- > arch/powerpc/mm/hugetlbpage.c | 42 ++ > 1 file changed, 42

Re: [PATCH 2/2] powerpc/book3s: mce: Use add_taint_no_warn() in machine_check_early().

Mahesh J Salgaonkar writes: > From: Mahesh Salgaonkar > > machine_check_early() gets called in real mode. The very first time when > add_taint() is called, it prints a warning which ends up calling opal > call (that uses OPAL_CALL wrapper)

Re: [PATCH v4] cxl: Force context lock during EEH flow

Frederic Barrat writes: > Le 05/04/2017 à 13:35, Vaibhav Jain a écrit : >> During an eeh event when the cxl card is fenced and card sysfs attr >> perst_reloads_same_image is set following warning message is seen in the >> kernel logs: >> >> [ 60.622727] Adapter

[BUG][next-20170410][PPC] WARNING: CPU: 22 PID: 0 at block/blk-core.c:2655 .blk_update_request+0x4f8/0x500

Hi, Warning while booting next-20170410 on PowerPC. We did not see warnings with next-20170407. In mean time I will update with the badcommit once my automated bisect run finishes. Machine type: Power7 LPAR Kernel : 4.11.0-rc6-next-20170410 Config : file attched. IPv6: ADDRCONF(NETDEV_UP):

Re: [PATCH v4] cxl: Force context lock during EEH flow

Le 11/04/2017 à 12:40, Michael Ellerman a écrit : Frederic Barrat writes: Le 05/04/2017 à 13:35, Vaibhav Jain a écrit : During an eeh event when the cxl card is fenced and card sysfs attr perst_reloads_same_image is set following warning message is seen in the

Re: [PATCH v2] ppc64/kprobe: Fix oops when kprobed on 'stdu' instruction

Thanks Balbir for the review, On Tuesday 11 April 2017 02:25 PM, Balbir Singh wrote: > On Tue, 2017-04-11 at 10:38 +0530, Ravi Bangoria wrote: >> If we set a kprobe on a 'stdu' instruction on powerpc64, we see a kernel >> OOPS: >> >> [ 1275.165932] Bad kernel stack pointer cd93c840 at

Re: WARN @lib/refcount.c:128 during hot unplug of I/O adapter.

Tyrel Datwyler writes: > On 04/06/2017 09:04 PM, Michael Ellerman wrote: >> Tyrel Datwyler writes: >> >>> On 04/06/2017 03:27 AM, Sachin Sant wrote: On a POWER8 LPAR running 4.11.0-rc5, a hot unplug operation on any I/O adapter

Re: [PATCH v3 2/5] perf/x86/intel: Record branch type

On Tue, Apr 11, 2017 at 04:11:21PM +0800, Jin, Yao wrote: > > > On 4/11/2017 3:52 PM, Peter Zijlstra wrote: > > This is still a completely inadequate changelog. I really will not > > accept patches like this. > > > Hi, > > The changelog is added in the cover-letter ("[PATCH v3 0/5] perf

Re: EEH error in doing DMA with PEX 8619

I did another test: - Call dma_set_mask_and_coherent(>dev, DMA_BIT_MASK(32)) in probe; - Use DMA address or BUS address in DMA But EHH error remains. All sources are based on PLX SDK 7.25. Note: Sample test is in user space. It allocates memory and starts DMA through PLX API. The original sample