Re: 1M hugepage size being registered on Linux

On Thu, 2017-06-22 at 13:59 +1000, Michael Ellerman wrote: > It's unsupported in Linux because it doesn't match the page table > geometry. > > We merged a patch from Aneesh to filter it out in 4.12-rc1: > >   a525108cf1cc ("powerpc/mm/hugetlb: Filter out hugepage size not supported > by page

Re: 1M hugepage size being registered on Linux

On Wed, 2017-06-21 at 20:33 +1000, Michael Ellerman wrote: > victora writes: > > > Hi Alistair/Jeremy, > > > > I am working on a bug related to 1M hugepage size being registered on > > Linux (Power 8 Baremetal - Garrison). > > Wasn't that caused by a firmware bug?

Re: [PATCH V4 2/2] powerpc/powernv : Add support for OPAL-OCC command/response interface

On Thu, 2017-06-22 at 09:57 +0530, Shilpasri G Bhat wrote: > Hi Cyril, > > On 06/22/2017 06:28 AM, Cyril Bur wrote: > > On Wed, 2017-06-21 at 13:36 +0530, Shilpasri G Bhat wrote: > > > In P9, OCC (On-Chip-Controller) supports shared memory based > > > commad-response interface. Within the shared

[PATCH backport pre-4.9] powerpc/slb: Force a full SLB flush when we insert for a bad EA

The SLB miss handler calls slb_allocate_realmode() in order to create an SLB entry for the faulting address. At the very start of that function we check that the faulting Effective Address (EA) is less than PGTABLE_RANGE (ignoring the region), ie. is it an address which could possibly fit in the

[RESEND PATCH V3] cxl: Export library to support IBM XSL

This patch exports a in-kernel 'library' API which can be called by other drivers to help interacting with an IBM XSL on a POWER9 system. The XSL (Translation Service Layer) is a stripped down version of the PSL (Power Service Layer) used in some cards such as the Mellanox CX5. Like the PSL, it

Re: Network TX Stall on 440EP Processor

On 6/21/17, Thomas Besemer wrote: > I'm working on a project that is derived from the Yosemite > PPC 440EP board. It's a legacy project that was running the > 2.6.24 Kernel, and network traffic was stalling due to transmission > halting without an understandable error

Re: 1M hugepage size being registered on Linux

On Wed, 2017-06-21 at 12:32 -0300, Mauricio Faria de Oliveira wrote: > On 06/21/2017 07:33 AM, Michael Ellerman wrote: > > > I am working on a bug related to 1M hugepage size being registered on > > > Linux (Power 8 Baremetal - Garrison). > > Wasn't that caused by a firmware bug? > > Ben/Stewart,

Re: [RFC v3 01/23] powerpc: Free up four 64K PTE bits in 4K backed HPTE pages

On Wed, 2017-06-21 at 18:39 -0700, Ram Pai wrote: > Rearrange 64K PTE bits to free up bits 3, 4, 5 and 6, > in the 4K backed HPTE pages. These bits continue to be used > for 64K backed HPTE pages in this patch, but will be freed > up in the next patch. The bit numbers are big-endian as >

[RFC PATCH 1/2] powerpc/xive: guest exploitation of the XIVE interrupt controller

This is the framework for using XIVE in a PowerVM guest. The support is very similar to the native one in a much simpler form. Instead of OPAL calls, a set of Hypervisors call are used to configure the interrupt sources and the event/notification queues of the guest: H_INT_GET_SOURCE_INFO

[RFC v2 0/3] powerpc/mm: Mark memory contexts requiring global TLBIs

capi2 and opencapi require the TLB invalidations being sent for addresses used on the cxl adapter or opencapi device to be global, as there's a translation cache in the PSL (for capi2) or NPU (for opencapi). The CAPP (for PSL) and NPU snoop the power bus. This is not new: for the hash memory

Re: [RFC v2 01/12] powerpc: Free up four 64K PTE bits in 4K backed hpte pages.

On 06/17/2017 09:22 AM, Ram Pai wrote: > Rearrange 64K PTE bits to free up bits 3, 4, 5 and 6 > in the 4K backed hpte pages. These bits continue to be used > for 64K backed hpte pages in this patch, but will be freed > up in the next patch. > > The patch does the following change to the 64K

[RFC PATCH 0/2] guest exploitation of the XIVE interrupt controller

Hello, I am currently working on a XIVE model for the pseries QEMU machine and I started hacking Linux to have something to test with. Here's a first draft of XIVE support for the guest. This is work in progress, only tested with the QEMU XIVE model I am working on. Feedback most welcome.

[RFC v2 1/3] powerpc/mm: Add marker for contexts requiring global TLB invalidations

Introduce a new 'flags' attribute per context and define its first bit to be a marker requiring all TLBIs for that context to be broadcasted globally. Once that marker is set on a context, it cannot be removed. Such a marker is useful for memory contexts used by devices behind the NPU and

Re: [PATCH v3 1/6] powerpc64/elfv1: Validate function pointer address in the function descriptor

Nicholas Piggin writes: > On Thu, 22 Jun 2017 00:08:37 +0530 > "Naveen N. Rao" wrote: > >> Currently, we assume that the function pointer we receive in >> ppc_function_entry() points to a function descriptor. However, this is >> not always the

Re: [PATCH 2/2] selftests/ftrace: Update multiple kprobes test for powerpc

On Thu, 22 Jun 2017 00:20:28 +0530 "Naveen N. Rao" wrote: > KPROBES_ON_FTRACE is only available on powerpc64le. Update comment to > clarify this. > > Also, we should use an offset of 8 to ensure that the probe does not > fall on ftrace location. The current

[RFC PATCH 2/2] powerpc/xive: add XIVE exploitation mode to CAS

On POWER9, the Client Architecture Support (CAS) negotiation process determines whether the guest operates in XIVE Legacy compatibility or in XIVE exploitation mode. Now that we have initial guest support for the XIVE interrupt controller, let's inform the hypervisor what we can do.

[linux-next][489e45][PowerPC] build broke on bare-metal with gcc 4.8.5

Hi, next-20170621 fails to build on PowerPC bare-metal with gcc 4.8.5 Test : build Machine : Power 8 bare-metal (BMC) kernel : 4.12.0-rc6 gcc : 4.8.5 config : Hab-NV-config $ make -S -j In file included from drivers/net/ethernet/qlogic/qede/qede.h:43:0, from

Re: [PATCH v3 4/6] powerpc/64s: Un-blacklist system_call() from kprobes

Nicholas Piggin writes: > On Thu, 22 Jun 2017 00:08:40 +0530 > "Naveen N. Rao" wrote: > >> It is actually safe to probe system_call() in entry_64.S, but only till >> we unset MSR_RI. To allow this, add a new symbol system_call_exit() >> after

Re: [PATCH 1/2] trace/kprobes: Sanitize derived event names

On Thu, 22 Jun 2017 00:20:27 +0530 "Naveen N. Rao" wrote: > When we derive event names, convert some expected symbols (such as ':' > used to specify module:name and '.' present in some symbols) into > underscores so that the event name is not rejected. Oops, ok,

Re: [next-20170619][a28e46f] WARNING: CPU: 5 PID: 1 at arch/powerpc/lib/feature-fixups.c:214 .check_features+0xa0/0xbc

Thanks for testing this configuration Abdul. Abdul Haleem writes: > Hi Michael, > > linux-next booted with warnings on a Power LPAR with CMO feature > enabled. > > Test : boot with CMO enabled > Kernel: 4.12.0-rc5-next-20170619 > gcc : 4.8.5 > Machine : Power 8

Re: 1M hugepage size being registered on Linux

On Tue, 20 Jun 2017 10:47:47 -0300 victora wrote: > Hi Alistair/Jeremy, > > I am working on a bug related to 1M hugepage size being registered on > Linux (Power 8 Baremetal - Garrison). > > I was checking dmesg and it seems that 1M page size is coming from >

Re: [PATCH V3] cxl: Export library to support IBM XSL

Christophe Lombard writes: > This patch exports a in-kernel 'library' API which can be called by > other drivers to help interacting with an IBM XSL on a POWER9 system. > > The XSL (Translation Service Layer) is a stripped down version of the > PSL (Power Service

[RFC v2 2/3] cxl: Mark context requiring global TLBIs

The PSL needs to see all TLBIs pertinent to the memory contexts used on the cxl adapter. For the hash memory model, it was done by making all TLBIs global as soon as the cxl driver is in use. For radix, we need something similar, but we can refine and only convert to global the invalidations for

[RFC v2 3/3] cxl: Add memory barrier to guarantee TLBI scope

With the hash memory model, all TLBIs become global when the cxl driver is active, i.e. as soon as one context is open. It is theoretically possible to send a TLBI with the wrong scope as there's currently no memory barrier between when the driver is marked as in use, and attaching a context to

Re: [PATCH v3 3/6] powerpc/64s: Blacklist system_call() and system_call_common() from kprobes

Nicholas Piggin writes: > On Thu, 22 Jun 2017 00:08:39 +0530 > "Naveen N. Rao" wrote: > >> Convert some of the symbols into private symbols and blacklist >> system_call_common() and system_call() from kprobes. We can't take a >> trap at parts

Re: [PATCH v3 5/6] powerpc/64s: Blacklist functions invoked on a trap

Nicholas Piggin writes: > On Thu, 22 Jun 2017 00:08:41 +0530 > "Naveen N. Rao" wrote: > >> Blacklist all functions involved while handling a trap. We: >> - convert some of the symbols into private symbols, >> - remove the duplicate 'restore'

Re: 1M hugepage size being registered on Linux

Benjamin Herrenschmidt writes: > On Thu, 2017-06-22 at 13:59 +1000, Michael Ellerman wrote: >> It's unsupported in Linux because it doesn't match the page table >> geometry. >> >> We merged a patch from Aneesh to filter it out in 4.12-rc1: >> >>   a525108cf1cc

Re: [RFC PATCH 1/2] powerpc/xive: guest exploitation of the XIVE interrupt controller

On Thu, 2017-06-22 at 11:29 +0200, Cédric Le Goater wrote: > This is the framework for using XIVE in a PowerVM guest. The support > is very similar to the native one in a much simpler form. Looks really good. Minor nits & comments... > Instead of OPAL calls, a set of Hypervisors call are used to

Re: [PATCH] powerpc: Only obtain cpu_hotplug_lock if called by rtasd

On Wed, 21 Jun 2017, Thiago Jung Bauermann wrote: > Michael Ellerman writes: > >> Notes: > >> This patch applies on tip/smp/hotplug, it should probably be carried > >> there. > > > > stop_machine_cpuslocked() doesn't exist in mainline so I think it has to > > be carried

Re: [PATCH] powerpc: Only obtain cpu_hotplug_lock if called by rtasd

Thiago Jung Bauermann writes: > Michael Ellerman writes: >> Thiago Jung Bauermann writes: >> >>> Calling arch_update_cpu_topology from a CPU hotplug state machine callback >>> hits a deadlock because the function

Re: [PATCH v3 4/6] powerpc/64s: Un-blacklist system_call() from kprobes

On Thu, 22 Jun 2017 21:14:21 +1000 Michael Ellerman wrote: > Nicholas Piggin writes: > > > On Thu, 22 Jun 2017 00:08:40 +0530 > > "Naveen N. Rao" wrote: > > > >> It is actually safe to probe system_call() in

DNS (?) not working on G5 (64-bit powerpc) (was [net-next, v3, 3/3] udp: try to avoid 2 cache miss on dequeue)

Paolo wrote: > when udp_recvmsg() is executed, on x86_64 and other archs, most skb > fields are on cold cachelines. > If the skb are linear and the kernel don't need to compute the udp > csum, only a handful of skb fields are required by udp_recvmsg(). > Since we already use skb->dev_scratch to

Re: [1/3] powerpc/64s: Use BRANCH_TO_COMMON() for slb_miss_realmode

On Tue, 2017-06-20 at 12:34:55 UTC, Michael Ellerman wrote: > All the callers of slb_miss_realmode currently open code the #ifndef > CONFIG_RELOCATABLE check and the branch via CTR in the RELOCATABLE case. > We have a macro to do this, BRANCH_TO_COMMON(), so use it. > > Signed-off-by: Michael

Re: [PATCH V3] cxl: Export library to support IBM XSL

Salut Christophe, Since there's a respin, 2 details below. diff --git a/drivers/misc/cxl/cxllib.c b/drivers/misc/cxl/cxllib.c new file mode 100644 index 000..4f4c5ca --- /dev/null +++ b/drivers/misc/cxl/cxllib.c @@ -0,0 +1,246 @@ +/* + * Copyright 2017 IBM Corp. + * + * This program is

Re: [PATCH v3 3/6] powerpc/64s: Blacklist system_call() and system_call_common() from kprobes

On Thu, 22 Jun 2017 21:07:46 +1000 Michael Ellerman wrote: > Nicholas Piggin writes: > > > On Thu, 22 Jun 2017 00:08:39 +0530 > > "Naveen N. Rao" wrote: > > > >> Convert some of the symbols into private symbols and

DPAA: Software Portal selection for network interface

Hello, as far as I understand the software portal selection for a network interface is done in static int dpaa_eth_probe(struct platform_device *pdev) { [...] channel = dpaa_get_channel(); if (channel < 0) { dev_err(dev, "dpaa_get_channel() failed\n"); err =

Re: [1/9] powerpc/64s: slb_allocate_realmode() preserve r3

On Sun, 2017-05-21 at 13:15:42 UTC, Nicholas Piggin wrote: > One fewer registers clobbered by this function means the SLB miss > handler can save one fewer. > > Signed-off-by: Nicholas Piggin Series applied to powerpc next, thanks.

Re: [PATCH V3] cxl: Export library to support IBM XSL

Le 22/06/2017 à 13:20, Michael Ellerman a écrit : Christophe Lombard writes: This patch exports a in-kernel 'library' API which can be called by other drivers to help interacting with an IBM XSL on a POWER9 system. The XSL (Translation Service Layer) is a

Re: [PATCH] dmaengine: fsldma: set BWC, DAHTS and SAHTS values correctly

On Mon, Jun 19, 2017 at 04:40:04PM +0200, Thomas Breitung wrote: > The bits of BWC, DAHTS and SAHTS in the DMA mode register must be cleared > before a new value can be or-ed in. Applied, thanks -- ~Vinod

Re: [PATCH v3 1/6] powerpc64/elfv1: Validate function pointer address in the function descriptor

On Thu, 22 Jun 2017 20:59:49 +1000 Michael Ellerman wrote: > Nicholas Piggin writes: > > > On Thu, 22 Jun 2017 00:08:37 +0530 > > "Naveen N. Rao" wrote: > > > >> Currently, we assume that the function pointer we

[PATCH V4] cxl: Export library to support IBM XSL

This patch exports a in-kernel 'library' API which can be called by other drivers to help interacting with an IBM XSL on a POWER9 system. The XSL (Translation Service Layer) is a stripped down version of the PSL (Power Service Layer) used in some cards such as the Mellanox CX5. Like the PSL, it

Re: [PATCH v3 1/6] powerpc64/elfv1: Validate function pointer address in the function descriptor

On 2017/06/22 11:06PM, Nicholas Piggin wrote: > On Thu, 22 Jun 2017 20:59:49 +1000 > Michael Ellerman wrote: > > > Nicholas Piggin writes: > > > > > On Thu, 22 Jun 2017 00:08:37 +0530 > > > "Naveen N. Rao" wrote: > > >

Re: [PATCH] of: update ePAPR references to point to Devicetree Specification

On Mon, Jun 19, 2017 at 03:23:41AM -0700, Frank Rowand wrote: > On 06/18/17 07:05, Rob Herring wrote: > > On Tue, Jun 13, 2017 at 07:49:04PM -0700, frowand.l...@gmail.com wrote: > >> From: Frank Rowand > >> > >> The Devicetree Specification has superseded the ePAPR as the >

RE: [PATCH 5/7] ntb: ntb_hw_intel: remove ioread64 and iowrite64 hacks

> -Original Message- > From: linux-...@googlegroups.com [mailto:linux-...@googlegroups.com] On > Behalf Of Logan Gunthorpe > Sent: Thursday, June 22, 2017 9:48 AM > To: linux-ker...@vger.kernel.org; linux-a...@vger.kernel.org; > linux-...@googlegroups.com; linux-al...@vger.kernel.org;

[PATCH 0/4] Reduce ELF_ET_DYN_BASE

This is a follow-up to "binfmt_elf: Use ELF_ET_DYN_BASE only for PIE"[1], which allow ELF_ET_DYN_BASE to be reduced from high in the address space. That patch only changed x86, and this series changes arm, arm64, powerpc, and s390. Since these depend on the mentioned patch (which I'm hoping akpm

[PATCH v2] of: update ePAPR references to point to Devicetree Specification

From: Frank Rowand The Devicetree Specification has superseded the ePAPR as the base specification for bindings. Update files in Documentation to reference the new document. First reference to ePAPR in Documentation/devicetree/bindings/arm/cci.txt is generic, remove it.

[PATCH] powerpc: Invalidate ERAT on powersave wakeup for POWER9

On POWER9 the ERAT may be incorrect on wakeup from some stop states that lose state. This causes random segvs and illegal instructions when these stop states are enabled. This patch invalidates the ERAT on wakeup on POWER9 to prevent this from causing a problem. Signed-off-by: Michael Neuling

[PATCH 3/4] powerpc: Reduce ELF_ET_DYN_BASE

Now that explicitly executed loaders are loaded in the mmap region, position PIE binaries lower in the address space to avoid possible collisions with mmap or stack regions. For 64-bit, align to 4GB to allow runtimes to use the entire 32-bit address space for 32-bit pointers. Signed-off-by: Kees

Re: [PATCH] Documentation: remove overlay-notes reference to non-existent file

On Tue, Jun 20, 2017 at 03:40:53PM -0700, frowand.l...@gmail.com wrote: > From: Frank Rowand > > File dt-object-internal.txt does not exist. Remove a reference to it > and fix up tags for references to other files. > > Reported-by: afaer...@suse.de > Signed-off-by: Frank

Re: [PATCH v3 6/6] powerpc/64s: Blacklist rtas entry/exit from kprobes

On 2017/06/22 01:48PM, Nicholas Piggin wrote: > On Thu, 22 Jun 2017 00:08:42 +0530 > "Naveen N. Rao" wrote: > > > We can't take traps with relocation off, so blacklist enter_rtas() and > > rtas_return_loc(). However, instead of blacklisting all of enter_rtas(), >

[PATCH 1/4] arm: Reduce ELF_ET_DYN_BASE

Now that explicitly executed loaders are loaded in the mmap region, position PIE binaries lower in the address space to avoid possible collisions with mmap or stack regions. Signed-off-by: Kees Cook --- arch/arm/include/asm/elf.h | 8 ++-- 1 file changed, 2

Re: [PATCH v2] of: update ePAPR references to point to Devicetree Specification

On Thu, Jun 22, 2017 at 09:15:39AM -0700, frowand.l...@gmail.com wrote: > From: Frank Rowand > > The Devicetree Specification has superseded the ePAPR as the > base specification for bindings. Update files in Documentation > to reference the new document. > > First

Re: [PATCH 1/2] trace/kprobes: Sanitize derived event names

On 2017/06/22 06:29PM, Masami Hiramatsu wrote: > On Thu, 22 Jun 2017 00:20:27 +0530 > "Naveen N. Rao" wrote: > > > When we derive event names, convert some expected symbols (such as ':' > > used to specify module:name and '.' present in some symbols) into > >

Re: [PATCH V4] cxl: Export library to support IBM XSL

Le 22/06/2017 à 15:07, Christophe Lombard a écrit : This patch exports a in-kernel 'library' API which can be called by other drivers to help interacting with an IBM XSL on a POWER9 system. The XSL (Translation Service Layer) is a stripped down version of the PSL (Power Service Layer) used in

Re: [RFC v3 01/23] powerpc: Free up four 64K PTE bits in 4K backed HPTE pages

On Thu, Jun 22, 2017 at 07:21:03PM +1000, Balbir Singh wrote: > On Wed, 2017-06-21 at 18:39 -0700, Ram Pai wrote: > > Rearrange 64K PTE bits to free up bits 3, 4, 5 and 6, > > in the 4K backed HPTE pages. These bits continue to be used > > for 64K backed HPTE pages in this patch, but will be

Re: [PATCH] powerpc: Only obtain cpu_hotplug_lock if called by rtasd

Michael Ellerman writes: > Thiago Jung Bauermann writes: > >> Michael Ellerman writes: >>> Thiago Jung Bauermann writes: >>> Calling arch_update_cpu_topology from a CPU hotplug state

Re: [RFC v2 01/12] powerpc: Free up four 64K PTE bits in 4K backed hpte pages.

On Thu, Jun 22, 2017 at 02:37:27PM +0530, Anshuman Khandual wrote: > On 06/17/2017 09:22 AM, Ram Pai wrote: > > Rearrange 64K PTE bits to free up bits 3, 4, 5 and 6 > > in the 4K backed hpte pages. These bits continue to be used > > for 64K backed hpte pages in this patch, but will be freed >

Re: [PATCH 2/2] selftests/ftrace: Update multiple kprobes test for powerpc

On 2017/06/22 06:07PM, Masami Hiramatsu wrote: > On Thu, 22 Jun 2017 00:20:28 +0530 > "Naveen N. Rao" wrote: > > > KPROBES_ON_FTRACE is only available on powerpc64le. Update comment to > > clarify this. > > > > Also, we should use an offset of 8 to ensure that

[PATCH 4/4] s390: Reduce ELF_ET_DYN_BASE

Now that explicitly executed loaders are loaded in the mmap region, position PIE binaries lower in the address space to avoid possible collisions with mmap or stack regions. For 64-bit, align to 4GB to allow runtimes to use the entire 32-bit address space for 32-bit pointers. Signed-off-by: Kees

[PATCH 2/4] arm64: Reduce ELF_ET_DYN_BASE

Now that explicitly executed loaders are loaded in the mmap region, position PIE binaries lower in the address space to avoid possible collisions with mmap or stack regions. For 64-bit, align to 4GB to allow runtimes to use the entire 32-bit address space for 32-bit pointers. Signed-off-by: Kees

Re: [next-20170609] WARNING: CPU: 3 PID: 71167 at lib/idr.c:157 idr_replace

On Thu, Jun 22, 2017 at 12:31:35AM +0100, Chris Wilson wrote: > Quoting Tejun Heo (2017-06-13 14:58:49) > > Cc'ing David Airlie. > > > > This is from drm driver calling in idr_replace() w/ a negative id. > > Probably a silly bug in error handling path? > > No, this is the validation of an

Re: [PATCH 01/17] cxlflash: Combine the send queue locks

> On Jun 21, 2017, at 9:13 PM, Uma Krishnan wrote: > > Currently there are separate spin locks for the two supported I/O queueing > models. This makes it difficult to serialize with paths outside the enqueue > path. > > As a design simplification and to support

Re: [PATCH] powerpc: Only obtain cpu_hotplug_lock if called by rtasd

On Thu, 22 Jun 2017, Thiago Jung Bauermann wrote: > Michael Bringmann provided this information: > >> It's not hard to backport both this patch and commit fe5595c07400 > >> ("stop_machine: Provide stop_machine_cpuslocked()") from branch > >> smp/hotplug in tip.git for stable. > > > > Yeah but it's

[PATCH 3/7] asm-generic/io.h: make ioread64 and iowrite64 universally available

Currently, ioread64 and iowrite64 are only available io CONFIG_64BIT=y and CONFIG_GENERIC_IOMAP=n. Thus, seeing the functions are not universally available, it makes them unusable for driver developers. This leads to ugly hacks such as those at the top of drivers/ntb/hw/intel/ntb_hw_intel.c This

[PATCH 7/7] crypto: caam: cleanup CONFIG_64BIT ifdefs when using io{read|write}64

Now that ioread64 and iowrite64 are always available we don't need the ugly ifdefs to change their implementation when they are not. Signed-off-by: Logan Gunthorpe Cc: "Horia Geantă" Cc: Dan Douglass Cc: Herbert Xu

Re: new dma-mapping tree, was Re: clean up and modularize arch dma_mapping interface V2

Hi all, On Wed, 21 Jun 2017 15:32:39 +0200 Marek Szyprowski wrote: > > On 2017-06-20 15:16, Christoph Hellwig wrote: > > On Tue, Jun 20, 2017 at 11:04:00PM +1000, Stephen Rothwell wrote: > >>

Re: [PATCH 02/17] cxlflash: Update cxlflash_afu_sync() to return errno

> On Jun 21, 2017, at 9:13 PM, Uma Krishnan wrote: > > The cxlflash_afu_sync() routine returns a negative one to indicate any kind > of failure. This makes it impossible to establish why the error occurred. > > Update the return codes to clearly indicate the failure

Re: [PATCH 08/17] cxlflash: Add scsi command abort handler

> On Jun 21, 2017, at 9:15 PM, Uma Krishnan wrote: > > To date, CXL flash devices do not support a single command abort operation. > Instead, the SISLite specification provides a context reset operation to > cleanup all pending commands for a given context. > > When

Re: [PATCH 3/7] asm-generic/io.h: make ioread64 and iowrite64 universally available

On Thu, 22 Jun 2017 14:24:58 -0600 Logan Gunthorpe wrote: > On 6/22/2017 2:14 PM, Alan Cox wrote: > > If a platform doesn't support 64bit I/O operations from the CPU then you > > either need to use some kind of platform/architecture specific interface > > if present or

Re: [PATCH 4/7] alpha: provide ioread64 and iowrite64 implementations

On 6/22/2017 3:03 PM, Arnd Bergmann wrote: Drivers that want a non-atomic variant should include either include/linux/io-64-nonatomic-hi-lo.h or include/linux/io-64-nonatomic-lo-hi.h depending on what they need. Drivers that require 64-bit I/O should probably just depend on CONFIG_64BIT and

Re: [PATCH 06/17] cxlflash: Track pending scsi commands in each hardware queue

> On Jun 21, 2017, at 9:14 PM, Uma Krishnan wrote: > > Currently, there is no book keeping of the pending scsi commands in the > cxlflash driver. This lack of tracking in-flight requests is too > restrictive and requires a heavy-hammer reset each time an adapter error

Re: [PATCH 4/7] alpha: provide ioread64 and iowrite64 implementations

On Thu, 22 Jun 2017 10:48:14 -0600 Logan Gunthorpe wrote: > Alpha implements its own io operation and doesn't use the > common library. Thus to make ioread64 and iowrite64 globally > available we need to add implementations for alpha. > > For this, we simply use calls that

Re: [PATCH 4/7] alpha: provide ioread64 and iowrite64 implementations

On Thu, Jun 22, 2017 at 10:09 PM, Logan Gunthorpe wrote: > On 6/22/2017 2:08 PM, Alan Cox wrote: >> >> But this does not do the same thing as an ioread64 with regards to >> atomicity or side effects on the device. The same is true of the other >> hacks. You either have a real

Re: [RFC PATCH 7/7 v1]powerpc: Deliver SEGV signal on protection key violation.

On Sat, Jun 17, 2017 at 08:54:44AM +1000, Benjamin Herrenschmidt wrote: > On Fri, 2017-06-16 at 12:15 -0700, Ram Pai wrote: > > gp_regs size is not changed, nor is the layout. A unused field in > > the gp_regs is used to fill in the AMR contents. Old binaries will not > > be knowing about this

[PATCH 2/7] iomap: implement ioread64 and iowrite64

Currently, ioread64 and iowrite64 are not impleminted in the generic iomap implementation. The prototypes are defined if CONFIG_64BIT is set but there is no actual implementation. Seeing the functions are not universally available, they are unusable for driver developers. This leads to ugly hacks

Re: [PATCH 4/7] alpha: provide ioread64 and iowrite64 implementations

> +#define iowrite64be(v,p) iowrite32(cpu_to_be64(v), (p)) Logan, thanks for taking this cleanup on. I think this should be iowrite64 not iowrite32? Stephen

Re: [PATCH 3/7] asm-generic/io.h: make ioread64 and iowrite64 universally available

On 6/22/2017 2:14 PM, Alan Cox wrote: If a platform doesn't support 64bit I/O operations from the CPU then you either need to use some kind of platform/architecture specific interface if present or accept you don't have one. Yes, I understand that. The thing is that every user that's

Re: DNS (?) not working on G5 (64-bit powerpc) (was [net-next, v3, 3/3] udp: try to avoid 2 cache miss on dequeue)

On Thu, Jun 22, 2017, at 22:57, Paolo Abeni wrote: > > Can you please check if the following patch fixes the issue? Only > compiled tested here. > > Thanks!!! > --- > diff --git a/net/ipv4/udp.c b/net/ipv4/udp.c > index 067a607..80d89fe 100644 > --- a/net/ipv4/udp.c > +++ b/net/ipv4/udp.c > @@

Re: [PATCH 04/17] cxlflash: Schedule asynchronous reset of the host

> On Jun 21, 2017, at 9:14 PM, Uma Krishnan wrote: > > A context reset failure indicates the AFU is in a bad state. At present, > when such a situation occurs, no further action is taken. This leaves the > adapter in an unusable state with no recoverable actions. > >

Re: [PATCH 05/17] cxlflash: Handle AFU sync failures

> On Jun 21, 2017, at 9:14 PM, Uma Krishnan wrote: > > AFU sync operations are not currently evaluated for failure. This is > acceptable for paths where there is not a dependency on the AFU being > consistent with the host. Examples include link reset events and LUN >

Re: [PATCH 3/7] asm-generic/io.h: make ioread64 and iowrite64 universally available

On Thu, 22 Jun 2017 10:48:13 -0600 Logan Gunthorpe wrote: > Currently, ioread64 and iowrite64 are only available io CONFIG_64BIT=y > and CONFIG_GENERIC_IOMAP=n. Thus, seeing the functions are not > universally available, it makes them unusable for driver developers. > This

[PATCH 0/7] cleanup issues with io{read|write}64

Hi, Presently, the 64bit IO functions are not very usable in drivers because they are not universally available in all architectures. This leads to a bunch of hacks in the kernel to work around this. (See the last 3 patches in this series.) As part of my switchtec_ntb submission which added

Re: [PATCH 4/7] alpha: provide ioread64 and iowrite64 implementations

On 6/22/2017 2:08 PM, Alan Cox wrote: But this does not do the same thing as an ioread64 with regards to atomicity or side effects on the device. The same is true of the other hacks. You either have a real 64bit single read/write from MMIO space or you don't. You can't fake it. Yes, I know.

Re: [PATCH 3/7] asm-generic/io.h: make ioread64 and iowrite64 universally available

On 6/22/2017 2:36 PM, Alan Cox wrote: I think that makes sense for the platforms with that problem. I'm not sure there are many that can't do it for mmio at least. 486SX can't do it and I guess some ARM32 but I think almost everyone else can including most 32bit x86. What's more of a problem is

Re: [PATCH 07/17] cxlflash: Flush pending commands in cleanup path

> On Jun 21, 2017, at 9:14 PM, Uma Krishnan wrote: > > When the AFU is reset in an error path, pending scsi commands can be > silently dropped without completion or a formal abort. This puts the onus > on the cxlflash driver to notify mid-layer and indicating that the

Re: [PATCH kernel 0/3 REPOST] vfio-pci: Add support for mmapping MSI-X table

On Thu, 15 Jun 2017 15:48:42 +1000 Alexey Kardashevskiy wrote: > Here is a patchset which Yongji was working on before > leaving IBM LTC. Since we still want to have this functionality > in the kernel (DPDK is the first user), here is a rebase > on the current upstream. > > >

[PATCH 4/7] alpha: provide ioread64 and iowrite64 implementations

Alpha implements its own io operation and doesn't use the common library. Thus to make ioread64 and iowrite64 globally available we need to add implementations for alpha. For this, we simply use calls that chain two 32-bit operations. (mostly because I don't really understand the alpha

[PATCH 5/7] ntb: ntb_hw_intel: remove ioread64 and iowrite64 hacks

Now that ioread64 and iowrite64 are available generically we can remove the hack at the top of ntb_hw_intel.c that patches them in when they are not available. Signed-off-by: Logan Gunthorpe Cc: Jon Mason Cc: Dave Jiang Cc: Allen

[PATCH 1/7] drm/tilcdc: don't use volatile with iowrite64

This is a prep patch for adding a universal iowrite64. The patch is to prevent compiler warnings when we add iowrite64 that would occur because there is an unnecessary volatile in this driver. Signed-off-by: Logan Gunthorpe Cc: Jyri Sarha Cc: Tomi Valkeinen

Re: DNS (?) not working on G5 (64-bit powerpc) (was [net-next,v3,3/3] udp: try to avoid 2 cache miss on dequeue)

On Thu, 2017-06-22 at 18:43 +0200, Paolo Abeni wrote: > On Thu, 2017-06-22 at 23:06 +1000, Michael Ellerman wrote: > > Paolo wrote: > > > when udp_recvmsg() is executed, on x86_64 and other archs, most skb > > > fields are on cold cachelines. > > > If the skb are linear and the kernel don't need

Re: [PATCH 03/17] cxlflash: Reset hardware queue context via specified register

> On Jun 21, 2017, at 9:14 PM, Uma Krishnan wrote: > > Per the SISLite specification, context_reset() writes 0x1 to the LSB of the > reset register. When the AFU processes this reset request, it is expected > to clear the bit after reset is complete. The current

Re: [PATCH 09/17] cxlflash: Create character device to provide host management interface

> On Jun 21, 2017, at 9:15 PM, Uma Krishnan wrote: > > The cxlflash driver currently lacks host management interface. Future > devices supported by cxlflash will provide a variety of host-wide > management functions. Examples include LUN provisioning, hardware debug >

[PATCH] powerpc/kernel: Avoid redundancies on giveup_all

Currently giveup_all() calls __giveup_fpu(), __giveup_altivec(), and __giveup_vsx(). But __giveup_vsx() also calls __giveup_fpu() and __giveup_altivec() again, in a redudant manner. Other than giving up FP and Altivec, __giveup_vsx() also disables MSR_VSX on MSR, but this is already done by

Re: [PATCH 4/7] alpha: provide ioread64 and iowrite64 implementations

On 06/22/2017 09:48 AM, Logan Gunthorpe wrote: Alpha implements its own io operation and doesn't use the common library. Thus to make ioread64 and iowrite64 globally available we need to add implementations for alpha. For this, we simply use calls that chain two 32-bit operations. (mostly

Re: DNS (?) not working on G5 (64-bit powerpc) (was [net-next,v3,3/3] udp: try to avoid 2 cache miss on dequeue)

On Thu, 2017-06-22 at 23:06 +1000, Michael Ellerman wrote: > Paolo wrote: > > when udp_recvmsg() is executed, on x86_64 and other archs, most skb > > fields are on cold cachelines. > > If the skb are linear and the kernel don't need to compute the udp > > csum, only a handful of skb fields are

[PATCH 6/7] drm/tilcdc: clean up ifdef hacks around iowrite64

Now that we can expect iowrite64 to always exist the hack is no longer necessary so we just call iowrite64 directly. Signed-off-by: Logan Gunthorpe Cc: Jyri Sarha Cc: Tomi Valkeinen Cc: David Airlie ---

Re: [PATCH 4/7] alpha: provide ioread64 and iowrite64 implementations

On 6/22/2017 11:29 AM, Stephen Bates wrote: +#define iowrite64be(v,p) iowrite32(cpu_to_be64(v), (p)) Logan, thanks for taking this cleanup on. I think this should be iowrite64 not iowrite32? Yup, good catch. Thanks. I'll fix it in a v2 of this series. Logan

Re: DNS (?) not working on G5 (64-bit powerpc) (was [net-next,v3,3/3] udp: try to avoid 2 cache miss on dequeue)

On Thu, 2017-06-22 at 23:06 +1000, Michael Ellerman wrote: > Paolo wrote: > > when udp_recvmsg() is executed, on x86_64 and other archs, most skb > > fields are on cold cachelines. > > If the skb are linear and the kernel don't need to compute the udp > > csum, only a handful of skb fields are

Re: 1M hugepage size being registered on Linux

Michal Suchánek writes: > On Tue, 20 Jun 2017 10:47:47 -0300 > victora wrote: > >> Hi Alistair/Jeremy, >> >> I am working on a bug related to 1M hugepage size being registered on >> Linux (Power 8 Baremetal - Garrison). >> >> I was checking

Re: [PATCH] powerpc: Invalidate ERAT on powersave wakeup for POWER9

On Fri, 2017-06-23 at 10:50 +1000, Stewart Smith wrote: > Michael Neuling writes: > > On POWER9 the ERAT may be incorrect on wakeup from some stop states > > that lose state. This causes random segvs and illegal instructions > > when these stop states are enabled. > > > > This

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